KEYWORDS: Field programmable gate arrays, Logic, Image compression, Optical engineering, Parallel processing, Binary data, Medical imaging, Wavelets, System on a chip, Video
This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial configurations of the arithmetic decoder, allows one to reduce the number of logic cells significantly (by 57%) in comparison with static implementation.
KEYWORDS: Digital signal processing, Image processing, Signal processing, Embedded systems, Neural networks, Video, Detection and tracking algorithms, Video processing, Facial recognition systems, Distance measurement
In this paper, we present implementations of a pattern recognition algorithm which uses a RBF (Radial Basis Function) neural network. Our aim is to elaborate a quite efficient system which realizes real time faces tracking and identity verification in natural video sequences. Hardware implementations have been realized on an embedded system developed by our laboratory. This system is based on a DSP (Digital Signal Processor) TMS320C6x. The optimization of implementations allow us to obtain a processing speed of 4.8 images (240 x 320 pixels) per second with a correct rate of 95% of faces tracking and identity verification.
KEYWORDS: Digital signal processing, Image processing, Neural networks, Signal processing, Embedded systems, Detection and tracking algorithms, Video, Data centers, Pattern recognition, Evolutionary algorithms
In this paper, we present implementations of a pattern recognition algorithm which uses a RBF (Radial Basis Function) neural network. Our aim is to elaborate a quite efficient system which realizes real time faces tracking and identity verification in natural video sequences. Hardware implementations have been realized on an embedded system developed by our laboratory. This system is based on a DSP (Digital Signal Processor) TMS320C6x. The optimization of implementations allow us to obtain a processing speed of 4.8 images (240x320 pixels) per second with a correct rate of 95% of faces tracking and identity verification.
KEYWORDS: Field programmable gate arrays, Image processing, Finite impulse response filters, Data processing, Digital filtering, Optical filters, Image acquisition, Signal processing, Image restoration, Analog electronics
FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGA's dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy , we realized an AT40K40 based board ARDOISE.
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