We report on the site-selective growth of >90% vertical GaAs nanowires (NWs) on Si (111) using self-assisted molecular beam epitaxy. The influences of growth parameters (pre-growth Ga opening time, V/III flux ratio) and processing conditions (reactive ion etching (RIE) and HF etching time) are investigated for different pitch lengths (200- 1000 nm) to achieve vertical NWs. The processing variables determine the removal of the native oxide layer and the contact angle of Ga-droplet inside the patterned hole that are critical to the vertical orientation of the NWs. Pre-growth Ga-opening time is found to be a crucial factor determining the size of the droplet in the patterned hole, while the V/III beam equivalent pressure (BEP) ratio influenced the occupancy of the holes due to the axial growth of NWs being group-V limited.
Ga assisted GaAs/GaAsSb core-shell structured nanowires were successfully grown on chemically etched p-type Si(111) substrate by molecular beam epitaxy (MBE). The morphology, structural and optical properties of the nanowires are found to be strongly influenced by the shell growth temperature and Sb% in the nanowires. The nanowires exhibit planar defects like twins and stacking faults, with more stacking faults and micro-twins found at the top section. Optical characteristics of the nanowires as measured by 4K photoluminescence (PL) exhibit a red shift to 1.2 eV with increasing Sb incorporation up to 12%. The Raman spectra of reference GaAs nanowires show TO and LO modes representative of the zinc blende structure at 291 cm-1 and 267.8 cm-1, respectively. Red shifts of both modes in conjunction with corresponding asymmetrical peak broadening observed in X-ray diffraction with increasing Sb incorporation are attributed to enhanced strain and disorder within the nanostructures. Nanowires of similar Sb composition but grown at different shell temperatures reveal straight nanowires with better microstructural and optical quality when grown at higher growth temperatures. The presence of GaAs passivation layer significantly enhanced the PL intensity such that PL was observed even at room temperature.
Low temperature gallium tin zinc oxide (GSZO) based thin film transistors fabricated on silicon has been investigated as a potential indium free transparent amorphous oxide semiconductor thin film transistor (TAOS TFT) with potential device applications on plastic substrates. A comprehensive and detailed study on the performance of GSZO TFTs has been carried out by studying the effects of processing parameters such as deposition temperature and annealing temperature/duration, as well as the channel thickness with all temperatures held below 150 °C. Variety of characterization techniques, namely Rutherford backscattering (RBS), x-ray photoelectron spectroscopy (XPS) and x-ray reflectivity (XRR) in addition to I-V and C-V measurements were employed to determine the effects of the above parameters on the composition and quality of the channel. Optimized TFT characteristics of ID=3×10-7 A, ION/OFF =2×106, VON ~ -2 V, SS ~ 1 V/dec and μFE = 0.14 cm2/V· s with a ΔVON of 3.3 V under 3 hours electrical stress were produced.
In this work the performance of bottom gate thin film transistors (TFTs) with transparent amorphous gallium tin zinc oxide (GSZO) active layers fabricated by radio frequency sputter deposition using a single GSZO target on SiO2/Si wafers will be presented. Trap density and its energetic distribution, and oxygen chemisorption were found to play a critical role in determining the operational characteristics of the device, all of which can be controlled by the oxygen incorporation and substrate temperature during deposition, along with the post-deposition annealing. In addition device instability, with respect to the electrical stress and optical illumination, can be suppressed by suitably tailoring these parameters. TFTs exhibiting a drain current (ID) of 10-6 A and on/off current ratio (Ion/off ) of 106 was achieved. A stable TFT has been achieved under electrical stress for 2% oxygen flow exhibiting ΔVT as low as ~0.5 V for 3hr stress under a gate bias of 1.2 and 12 V, with good optical stability.
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