Semiconductor manufacturing’s full chip RET/OPC operations rely on the process models calibrated against metrology data collected from custom designed test structures. Physics-based compact models and machine learning models inherently carry the issue of model coverage often synonymous with calibration test pattern coverage. Therefore, process models frequently fail to predict unseen patterns within error tolerance. With the push for advanced technology node, such events can even occur after a node is declared HVM ready. Foundries have been combating the model coverage deficiency through costly model revisions, or expensive repair flows. There has always been the desire to have capability to screen and enhance compact model of potential coverage issue. In this paper, we use the machine learning clustering platform to learn the signatures of the model calibration test patterns and then compare them to the new design patterns in terms of feature vectors’ space correlated to model parameters’ space. The comparison provides not only the locations of the new patterns but also the similarity ranking with respect to the reference pattern, so that those patterns can be included and be further analyzed for better model coverage. These patterns are often suitable candidates to be included into new model calibration set. In this application, full chip capability is also essential besides the accuracy of the learning. The full-chip pattern check needs to be done quickly and efficiently; hence this technology could be adopted for new chip screening, highlighting areas worth paying extra attention to during inspection.
For increasingly small and dense designs requiring adequate DOF, MEEF, and EL, numerous technologies have been
employed to increase yield. Some techniques such as process optimization (i.e. SMO) are effective, but can be costly and
time consuming, and are not easily modifiable once an initial choice is made. Design optimization can be done
separately from knowledge of the fab's OPC correction, but for sub 32nm nodes the complexity and interaction of the
design target shapes is becoming too complicated for predefined design rules to produce an acceptable result.
In this paper we introduce a method called Lithographically Enhanced Edge Design (LEED) suited for IDMs. This joint
target and mask optimization method takes into account the full OPC correction and process, and modifies the user's
design in a controlled way so as to produce a new design with improved lithographic performance which can be used in
place of the initial design. Control is given to the user so that inter-layer dependencies are not broken. Also, integrated
target, mask, and source optimization is available in cases where target and mask optimization in not sufficient to
produce adequate results. The use of ILT allows efficient target, mask, and source correction without extensive user
OPC scripting and target modification sweeping. We show LEED results which enable production at 20x node.
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