We have developed multi-field imprint (MFI) technology to improve the productivity of for nano-imprint lithography (NIL). Using a template having an imprinting size of 46 mm × 28 mm for MFI and the latest NIL system NZ2C (Canon Corp.), we successfully achieved MFI on a 300-mm wafer. The throughput being equivalent to 160 wafers per hour was demonstrated using throughput enhancement solutions, such as gas permeable spin-on-carbon and multi field dispense. The overlay accuracy around 7 nm was also obtained. In this report, we’ll report about the performance of MFI technology: patterning ability, throughput, and overlay accuracy, and discuss the future outlook.
We have developed Multi-Field Imprint (MFI) technology to improve the productivity of for nano-imprint lithography (NIL). Using the template having the imprinting size of 46 mm x 28 mm for MFI and the latest NIL system NZ2C (Canon Corp.), we successfully achieved multi-field imprinting on a 300 mm wafer. The throughput being equivalent to 160 wafers per hour was demonstrated using throughput enhancement solutions, such as gas permeable spin-on-carbon and multi field dispense. The overlay accuracy around 7 nm was also obtained. In this report, we’ll report about the performance of MFI technology: patterning ability, throughput, and overlay accuracy and discuss the future outlook.
Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. To apply smaller pattern size device, layout dependent hotspots becomes a significant issue, so design for manufacturing (DFM) flow considering imprint process has to be prepared. In this paper, focused on fine resist spread, RLT (Residual Layer Thickness) uniformity improvement utilizing simulation is demonstrated and resist drop compliance check flow is proposed
Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.
Directed self-assembly (DSA) of block copolymers (BCPs) is a promising method for producing the sub-20nm features
required for future semiconductor device scaling, but many questions still surround the issue of defect levels in DSA
processes. Knowledge of the free energy associated with a defect is critical to estimating the limiting equilibrium defect
density that may be achievable in such a process. In this work, a coarse grained molecular dynamics (MD) model is used
to study the free energy of a dislocation pair defect via thermodynamic integration. MD models with realistic potentials
allow for more accurate simulations of the inherent polymer behavior without the need to guess modes of molecular
movement and without oversimplifying atomic interactions. The free energy of such a defect as a function of the Flory-
Huggins parameter (χ) and the total degree of polymerization (N) for the block copolymer is also calculated. It is found
that high pitch multiplying underlayers do not show significant decreases in defect free energy relative to a simple pitch
doubling underlayer. It is also found that χN is not the best descriptor for correlating defect free energy since
simultaneous variation in chain length (N) and χ value while maintaining a constant χN product produces significantly
different defect free energies. Instead, the defect free energy seems to be directly correlated to the χ value of the diblock
copolymer used. This means that as higher χ systems are produced and utilized for DSA, the limiting defect level will
likely decrease even though DSA processes may still operate at similar χN values to achieve ever smaller feature sizes.
Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is a promising candidate for extremely low-cost fabrication of large-area devices in large volumes. A residual layer thickness (RLT) of a pattern transferred by RtR-NIL distributes at around several micrometers or more. We tried to thin the RLT below 100 nm and confirmed the controllability of the RLT and its deviation in the patterned sample.
Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning
technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is promising candidate for extremely low-cost fabrication of large-area devices in large volumes. We have tried to transfer sub-100 nm patterns, especially sub-30 nm patterns, onto ultraviolet (UV) curable resin on film substrate by RtR-NIL. We demonstrate a 24 nm pattern on a film substrate by RtR-NIL and the method's potential for sub-100 nm patterning.
The actual extreme ultraviolet lithography tools will have aberrations around seven times larger than those of the latest ArF lithography tools in wavelength normalized rms. We calculated the influence of aberrations on the size error and pattern shift error using Zernike sensitivity analysis. Mask-induced aberration restricts the specification of aberration. Without periodic additional pattern, the aberration level that can be accepted to form 22 nm dual-gate patterns was <8 m rms. Arranging the periodic additional pattern relaxed the aberration tolerance. With periodic additional pattern, the acceptable aberration level to form 22 nm patterns was below <37 m rms. It is important to make pattern periodicity for the relaxation of the aberration specification.
Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch
of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography
technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by
means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test
pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by
etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22-
nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on
yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer
process for device manufacture at the 22-nm node and beyond.
We introduce techniques of flare compensation for Extreme Ultraviolet Lithography that can reduce the calculation time
of a flare map and flare correction. In the first approach, the range of a flare point spread function is divided into several
regions and the size of meshes for the flare map in each region is selected. In the second approach, the size of the mask
pattern is controlled by referring to the flare map in the mask-making process. In the third approach, dosage of each
point in a mask corresponding to the flare map is modulated when transferring the mask pattern onto the resist. Use of
these approaches in the proper combination is effective for TAT reduction and accuracy of the flare compensation.
This work concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacturing based on accelerated development in critical areas, and the construction of a process liability (PL) test site that integrates results in these areas. Overall lithography performance is determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. The effect of flare on CD variation is a critical issue in EUVL, so flare is compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that take resist blur into account. Production readiness of EUVL based on the integration of results in these areas is evaluated by electrical tests on low-resistance tungsten wiring. We find the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.
We estimated aberrations using Zernike sensitivity analysis. We found the difference of the tolerated aberration with line
direction for illumination. The tolerated aberration of perpendicular line for illumination is much smaller than that of
parallel line. We consider this difference to be attributable to the mask 3D effect. We call it mask-induced aberration. In
the case of the perpendicular line for illumination, there was a difference in CD between right line and left line without
aberration. In this report, we discuss the possibility of pattern formation in NA 0.25 generation EUV lithography tool. In
perpendicular pattern for EUV light, the dominant part of aberration is mask-induced aberration. In EUV lithography,
pattern correction based on the mask topography effect will be more important.
This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on
accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in
these areas. The overall lithography performance was determined from the performance of the exposure tool, the
printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction
technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33
mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus,
the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation
of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on
CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the
projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an
electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal
wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of
EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten
wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were
found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We
found the PL test site to be very useful for determining where further improvements need to be made and for evaluating
the production readiness of EUVL.
It seems that the actual EUV lithography tools will have aberrations around ten times larger than those of the
latest ArF lithography tools in wavelength normalized rms. We calculated the influence of aberrations on the size error
and pattern shift error using Zernike sensitivity analysis. Mask-induced aberration restricts the specification of aberration.
Without periodic additional pattern, the aberration to form 22 nm dual-gate patterns was below 8 mλ rms. Arranging the
periodic additional pattern relaxed the aberration tolerance. With periodic additional pattern, the aberration to form 22
nm patterns was below 37 mλ rms. It is important to make pattern periodicity for the relaxation of the aberration
specification.
KEYWORDS: Electron beam direct write lithography, Line width roughness, Electron beams, Silicon, Data conversion, Beam shaping, Vestigial sideband modulation, Photoresist processing, System integration, Logic devices
We have developed a character projection (CP)-type low-energy electron beam (EB) direct writing (EBDW) system
called EBIS (Electron Beam Integrated System). A low-energy EB of less than 5 keV has the potential to expose by the
CP-method without intra- and inter-layer proximity effect corrections. In this paper, the advantages of the proximity
effect of the low-energy EBDW system of 5 keV with the CP exposure are discussed. The experimental results to
compare the intra-layer proximity effect between 5 keV and 50 keV showed that the low-energy EB has an advantage
over high-energy EB in terms of small shot size deviation at the pattern edge. The experimental results of inter-layer
proximity effect of 5 keV indicate that no proximity effect corrections for structures in underlying layers are necessary
in the case of the combination of low-energy EB and multi-layer resist. On the other hand, in response to concern about
the Coulomb interaction effect, which is a critical problem of low-energy EB, a dose correction function of each shot
was proposed for the EBIS system. We are convinced that the low-energy EBDW is useful for exposure of practical
patterns of logic devices by the CP exposure with higher throughput, because the proximity effect is so small that
complicated corrections due to the adjacent pattern and structures of substrate under exposure layer are unnecessary.
KEYWORDS: Vestigial sideband modulation, Data conversion, Metals, Electron beams, Databases, Front end of line, Back end of line, Electron beam direct write lithography, Lithography, Logic devices
The EBIS data conversion system has been developed to be optimized for layout data of logic devices with Character Projection (CP) method. In the system, standard cells and memory cells are registered into a character database as keeping the hierarchy of cell pattern in the device pattern, so that a common CP aperture can be created for several logic devices. The order of EB shots are optimized to shorten the time of writing the patterns, small shots (sliver shots) create as few as possible, and the total number of EB shots are minimized for a specified CP aperture. The system was evaluated by processing ASIC devices of hp 180 nm, 130 nm and 90 nm nodes. The average processing time is about 1 hour with the average number of EB shots of 50 × 106 per a chip. The reduction rates of the number of shots from only conventional Variably Shaped Beam (VSB) to with CP were estimated about 80%, 45%, and 80% for the layers of front-end-of-line (FEOL), metal and via layers of back-end-of-line (BEOL), respectively.
The character projection is utilized for maskless lithography and is a potential for the future photomask manufacture. The drawback of the character projection is its low throughput and leads to a price rise of ICs. This paper discusses a technology mapping technique for enhancing the throughput of the character projection. The number of EB shots to draw an entire chip determines the fabrication time for the chip. Reduction of the number of EB shots, therefore, increases the throughput of character projection equipment and reduces the cost to produce ICs. Our technology mapping technique aims to reduce the number of EB shots to draw an entire chip for increasing the throughput of character projection equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with an conventional technology mapping, our technology mapping technique achieved 19.6% reduction of the number of EB shots without any performance degradation of ICs. Moreover, our technology mapping technique achieved 48.8% reduction of the number of EB shots under no
performance constraints. Our technique is easy for both IC designers and equipment developers to adopt because it is a software approach with no additional modification on character projection equipment.
KEYWORDS: Back end of line, Vestigial sideband modulation, Logic devices, Metals, Data processing, Photomasks, Electron beams, Electron beam direct write lithography, Computer aided design, Beam shaping
Electron beam direct writing (EBDW) system is at the head of systems fabricating circuit patterns by maskless. But the throughput of EBDW is very poor beause very large number of electron beam (EB) shots are requested for exposure of whole patterns on a wafer. We had proposed methods of reduction of the number of EB shots with Character Projection (CP) and designing the best devicve pattern for CP-EBDW to fabricate logic devices such as ASIC or SoC device. Though the method is effective to Front-End-Of-Line (FEOL) layers of cell based logic deviec, Back-End-Of-Line (BEOL) layers cannot be exposed by the method with small number of characters and EB shots. Now, we will propose methods for appropriate CP exposure and data processign for patterns in BEOL layers. By the methods, each BEOL layer in a typical logic device cna be exposed with throughputs about 6 to 8 wafers/h, with a Low-energy-EBDW system produced by e-BEAM Corporation, named "EBIS".
KEYWORDS: Scanning electron microscopy, Virtual colonoscopy, System on a chip, Logic devices, Maskless lithography, Lenses, Semiconducting wafers, Inspection, Electron beam direct write lithography, Lithography
In order to realize SoC (System on a Chip) fabrication at low cost with quick-TAT (Turn-Around-Time) we have proposed a maskless lithography (ML2) strategy, a low-energy electron-beam direct writing (LEEBDW) system with a common character projection (CP) aperture. This paper presents a status report on our proof-of-concept (POC) system. We have developed a compact EB column consisting small electrostatic lenses and deflectors. The experimental results for our POC system indicated that the patterns corresponding to 50nm-node logic devices can be obtained with CP exposure at the incident energy of 5 keV. The technique to reduce the raw process time using a SEM function of LEEBDW system is also reported.
Ultrathin films in the thickness range of 2-10 nm were deposited by plasma polymerization. An AFM (atomic force microscope) was used to evaluate the film surface uniformity. The measured surface roughness of these films is of the order of 0.1 to 0.3 nm. It suggests that uniformly smooth, pinhole free ultra thin film organic films suitable for electronic applications can be deposited by plasma polymerization. The deposited films were tested for nanometer scale patterning using an atomic force microscope. Process of contact electrification was used to deposit local electric charge on these surface enhanced reactions with some adsorbates thus creating patterns.
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