KEYWORDS: Optical alignment, Electron beam direct write lithography, Electron beams, Overlay metrology, Control systems, Semiconducting wafers, Metals, Back end of line, Backscatter, Electron beam lithography
Techniques to appropriately control the key factors for a character projection (CP) based electron beam direct writing technology for mass production are shown and discussed. In order to achieve accurate CD control, the CP technique using the master CP is adopted. Another CP technique, the Packed CP, is used to obtain suitable shot count. For the alignment on the some critical layers which normally have an even surface, the process removing SiO2 material filled in the alignment marks is added and then the alignment marks can be detected using electron beam. The proximity effect correction using the simplified electron energy flux model and the hybrid exposure are used to obtain enough process margins. As a result, the sufficient CD accuracy, overlay accuracy, and yield are obtained on the 65 nm node device. Due to the proper system control, more than 10,000 production wafers have been successfully exposed so far without any major system downtime. It is shown that those techniques can be adapted to the 32 nm node production with slight modifications. It is expected that by using the Multi Column Cell exposure method, those techniques will be applicable to the rapid establishment for the 14 nm node technology.
KEYWORDS: Electron beam direct write lithography, Optical alignment, Electron beams, Control systems, Semiconducting wafers, Overlay metrology, Metals, Photoresist processing, Backscatter, Electron beam lithography
Techniques to appropriately control the key factors for a character projection (CP) based electron beam direct writing
(EBDW) technology for mass production are shown and discussed. In order to achieve accurate CD control, the CP
technique using the master CP is adopted. Another CP technique, the Packed CP, is used to obtain suitable shot count.
For the alignment on the some critical layers which have the normally an even surface, the alignment methodology differ
from photolithography is required. The process that etches the SiO2 material in the shallow trench isolation is added and
then the alignment marks can be detected using electron beam even at the gate layer, which is normally on an even
surface. The proximity effect correction using the simplified electron energy flux model and the hybrid exposure are used
to obtain enough process margins. As a result, the sufficient CD accuracy, overlay accuracy, and yield are obtained on the
65 nm node device. The condition in our system is checked using self-diagnosis on a regular basis, and scheduled
maintenances have been properly performed. Due to the proper system control, more than 10,000 production wafers have
been successfully exposed so far without any major system downtime. It is shown that those techniques can be adapted
to the 32 nm node production with slight modifications. For the 14 nm node and beyond, however, the drastic increment
of the shot count becomes more of a concern. The Multi column cell (MCC) exposure method, the key concept of which
is the parallelization of the electron beam columns with a CP, can overcome this concern. It is expected that by using the
MCC exposure system, those techniques will be applicable to the rapid establishment for the 14 nm node technology.
The computer cost for mask data processing grows increasingly more expensive every year.
However the Graphics Processing Unit (GPU) has evolved dramatically. The GPU which
originally was used exclusively for digital image processing has been used in many fields of
numerical analysis. We developed mask data processing techniques using GPUs together with
distributed processing that allows reduced computer costs as opposed to a distributed processing
system using just CPUs.
Generally, for best application performance, it is important to reduce conditional branch
instructions, to minimize data transfer between the CPU host and the GPU device, and to optimize
memory access patterns in the GPU. Hence, in our optical proximity correction (OPC), the light
intensity calculation step, that is the most time consuming part of this OPC, is optimized for GPU
implementation and the other inefficient steps for GPU are processed by CPUs . Moreover, by
fracturing input data and balancing a computational road for each CPU, we have put the powerful
distributed computing into practice.
Furthermore we have investigated not only the improvement of software performance but also how
to best balance computer cost and speed, and we have derived a combination of the CPU hosts and
the GPU devices to maximize the processing performance that takes computer cost into account .
We have also developed a recovery function that continues OPC processing even if a GPU breaks
down during mask data processing for a production. By using the GPUs and distributed
processing, we have developed a mask data processing system which reduces computer cost and has
high reliability.
Phase shifter edge lithography (double-exposure method) provides improved image contrast and lithographic resolution. However, it is subject to the problems of optical proximity effects. Therefore, to make this technique practical for use in device manufacturing, it is necessary to understand the characteristics of optical proximity effects and through such understanding establish a practical OPC (Optical Proximity Correction) method to correct them. Since the size of both the phase shift mask (PSM) and the trim mask (a mask used to form a rough gate pattern) significantly affect the wafer CD (critical dimension), an OPC tool which takes the layout of the two masks into account is required. Due to the difficulty in describing a rule-table for both masks, a model-based approach is a suitable means to develop such a tool. A PSM and a trim mask are used to calculate aerial images. In a double-exposure approach, however, mask shape does not define the desired shape. Therefore, an additional layer which defines the desired shape has been introduced. The desired shape is also used to consider the etching effect, which is described in a rule-table and applied to the original layout. With this approach, the desired shape defines the resist shape. To improve computing time, we apply model-based OPC only to specified areas, and rule-based OPC outside of those areas. Because of the large amount of data that must be processed, the designed layout is divided into fractions and compute on a multi-processor system. Previously, we reported improvements in pattern-matching methods to reduce the simulation time. In this paper, we report full-chip- correction performance and results of OPC technology.
Alternate-type phase shifting masks (PSMs) have been investigated as a methods used to fabricate 0.18 micrometer and smaller rule devices. For practical use, an automatic shifter placement CAD, a DRC for the indicating errors in rules for alternate-type PSMs, and an optical proximity correction (OPC) tool are indispensable. We previously reported on the algorithm for the shifter placement and the DRC for alternate-type PSMs and the OPC tool. We now report that these tools enhance the practical CAD system, fully supporting the entire process from designing the physical layout to adjusting the mask patterns in order to prevent the optical proximity effects. First, the phase shifting patterns are generated automatically. Next, the DRC tool indicates rule errors for the design of alternate-type PSMs. The Designers must modify the indicated portions and replace the shifters or DRC until there are no errors. In order to be more general than our previous tools, it is important that the delivering data between the layout editor and the program be GDS formatted data. Following the designing of the PSMs, the OPC tool, which was developed on parallel processor units, adjusts the designed patterns. Our system was actually used to fabricate 0.18 micrometer rule full-chip devices, and thus we confirmed that the computing performance is satisfactorily practical and that the CAD system shows promises as a means of fabricating rule devices beyond current rules.
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