Dr. Paul Friedberg Profile

Dr. Paul Friedberg

Staff Corporate Applications Engineer at Synopsys Inc

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Publications (9)

Proceedings Article | 12 April 2013 Paper

An investigation into scalability and compliance for triple patterning with stitches for metal 1 at the 14nm node

Christopher Cork, Alexander Miloslavsky, Paul Friedberg, Gerry Luk-Pat

Proceedings Volume 8683, 868308 (2013) https://doi.org/10.1117/12.2011548

KEYWORDS: Optical lithography, Metals, Photomasks, Double patterning technology, Lithography, Extreme ultraviolet lithography, Extreme ultraviolet, Legal, Network architectures, Fractal analysis

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Lithographers had hoped that single patterning would be enabled at the 20nm node by way of EUV lithography. However, due to delays in EUV readiness, double patterning with 193i lithography is currently relied upon for volume production for the 20nm node’s metal 1 layer. At the 14nm and likely at the 10nm node, LE-LE-LE triple patterning technology (TPT) is one of the favored options [1,2] for patterning local interconnect and Metal 1 layers. While previous research has focused on TPT for contact mask, metal layers offer new challenges and opportunities, in particular the ability to decompose design polygons across more than one mask. The extra flexibility offered by the third mask and ability to leverage polygon stitching both serve to improve compliance. However, ensuring TPT compliance – the task of finding a 3-color mask decomposition for a design – is still a difficult task. Moreover, scalability concerns multiply the difficulty of triple patterning decomposition which is an NP-complete problem. Indeed previous work shows that network sizes above a few thousand nodes or polygons start to take significantly longer times to compute [3], making full chip decomposition for arbitrary layouts impractical. In practice Metal 1 layouts can be considered as two separate problem domains, namely: decomposition of standard cells and decomposition of IP blocks. Standard cells typically include only a few 10’s of polygons and should be amenable to fast decomposition. Successive design iterations should resolve compliance issues and improve packing density. Density improvements are multiplied repeatedly as standard cells are placed multiple times. IP blocks, on the other hand, may involve very large networks. This paper evaluates multiple approaches to triple patterning decomposition for the Metal 1 layer. The benefits of polygon stitching, in particular, the ability to resolve commonly encountered non-compliant layout configurations and improve packing density, are weighed against the increased difficulty in finding an optimized, legal decomposition and coping with the increased scalability challenges.

Proceedings Article | 28 March 2007 Open Access

Collaborative platform, tool-kit, and physical models for DfM

Andy Neureuther, Wojtek Poppe, Juliet Holwill, Eric Chin, Lynn Wang, Jae-Seok Yang, Marshal Miller, Dan Ceperley, Chris Clifford, Koji Kikuchi, Jihong Choi, Dave Dornfeld, Paul Friedberg, Costas Spanos, John Hoang, Jane Chang, Jerry Hsu, David Graves, Alan Wu, Mike Lieberman

Proceedings Volume 6521, 652104 (2007) https://doi.org/10.1117/12.721199

KEYWORDS: Design for manufacturing, Photomasks, Device simulation, Computer aided design, Process modeling, Etching, Monochromatic aberrations, Manufacturing, Lithography, Chemical mechanical planarization

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Proceedings Article | 28 March 2007 Paper

Transistor-based electrical test structures for lithography and process characterization

Wojtek Poppe, Juliet Holwill, Liang-Teck Pang, Paul Friedberg, Qingguo Liu, Louis Alarcon, Andrew Neureuther

Proceedings Volume 6520, 65203N (2007) https://doi.org/10.1117/12.711613

KEYWORDS: Transistors, Line width roughness, Lithography, Critical dimension metrology, Databases, Semiconducting wafers, Structural design, Cryogenics, Photomasks, Metals

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Proceedings Article | 21 March 2007 Paper

Modeling spatial gate length variation in the 0.2µm to 1.15mm separation range

Paul Friedberg, Willy Cheung, George Cheng, Qian Ying Tang, Costas Spanos

Proceedings Volume 6521, 652119 (2007) https://doi.org/10.1117/12.710668

KEYWORDS: Critical dimension metrology, Molybdenum, Manufacturing, Monte Carlo methods, Structural design, Etching, Metrology, Process control, Lithography, Resistance

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Proceedings Article | 21 March 2007 Paper

Circuit size optimization with multiple sources of variation and position dependant correlation

Qian Ying Tang, Paul Friedberg, George Cheng, Costas Spanos

Proceedings Volume 6521, 65210P (2007) https://doi.org/10.1117/12.711794

KEYWORDS: Transistors, Performance modeling, Semiconducting wafers, Monte Carlo methods, Instrument modeling, Statistical modeling, Distance measurement, Computer programming, Device simulation, Capacitance

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Proceedings Article | 15 March 2006 Paper

Spatial modeling of micron-scale gate length variation

Paul Friedberg, Willy Cheung, Costas Spanos

Proceedings Volume 6155, 61550C (2006) https://doi.org/10.1117/12.656521

KEYWORDS: Critical dimension metrology, Monte Carlo methods, Statistical analysis, Process control, Semiconducting wafers, Data modeling, Device simulation, Statistical modeling, Picosecond phenomena, Performance modeling

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Proceedings Article | 5 May 2005 Paper

Modeling within-field gate length spatial variation for process-design co-optimization

Paul Friedberg, Yu Cao, Jason Cain, Ruth Wang, Jan Rabaey, Costas Spanos

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600028

KEYWORDS: Process control, Critical dimension metrology, Monte Carlo methods, Lithography, Manufacturing, Data modeling, Metrology, Semiconducting wafers, Performance modeling, Device simulation

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Pelgrom's model suggests that a spatial correlation structure is inherent in the physical properties of semiconductor devices; specifically, devices situated closely together will be subject to a higher degree of correlation than devices separated by larger distances. Since correlation of device gate length values caused by systematic variations in microlithographic processing is known to carry a significant impact on the variability of circuit performance, we attempt to extract and understand the nature of spatial correlation across an entire die. Based on exhaustive, full-wafer critical dimension measurements collected using electrical linewidth metrology for wafers processed in a standard 130nm lithography cell, we calculate a spatial correlation metric of gate length over a full-field range in both horizontal and vertical orientations. Using a rudimentary model fit to these results, we investigate the impact of correlation in the spatial distribution on the variability of circuit performance using a series of Monte Carlo analyses in HSPICE; it is confirmed that this correlation does indeed present a significant influence on performance variability. From the same dataset, we also extract both the across-wafer (AW) and within-field (WIF) contributions to systematic variation. We find that the spatial correlation model’s shape is strongly related to these two components of variation (both in magnitude as well as by spatial fingerprint). By artificially reducing each of these components of systematic variation-thereby simulating the effects of active, across-field process compensation-we show that spatial correlation is significantly reduced, nearly to zero. This implies that Pelgrom's model may not apply to die-scale separation distances, and that a more accurate correlation theory would combine Pelgrom's model over very short separation distances with a systematic variation model that captures variability over longer distances by means of non-stationary distributions.

Proceedings Article | 24 May 2004 Paper

Time-based PEB adjustment for optimizing CD distributions

Paul Friedberg, Cherry Tang, Bhanwar Singh, Thomas Brueckner, Wolfram Gruendke, Bernd Schulz, Costas Spanos

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.535871

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Temperature metrology, 193nm lithography, Photoresist materials, Scatterometry, Data modeling, Lithography, Sensors, Thermal effects

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Proceedings Article | 24 May 2004 Paper

Across-wafer CD uniformity enhancement through control of multizone PEB profiles

Qiaolin Zhang, Paul Friedberg, Cherry Tang, Bhanwar Singh, Kameshwar Poolla, Costas Spanos

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.537121

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Data modeling, Temperature metrology, Control systems, Lithography, Etching, Metrology, Process control, Thermal modeling

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Showing 5 of 9 publications

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