The end of Moore’s law scaling represents a major paradigm change for the semiconductor industry. Value-add will no longer defined simply by technology but by custom design and architecture solutions for specific applications. This represents a shift in business model to a larger number of more custom designs fabricated in lower volumes. This shift will be discussed together with potential new applications for such low volume chips.
We analyze the performance and process latitudes of a high-throughput, all-optical lithography method that addresses the requirements of the 32-nm node. This hybrid scheme involves a double exposure and only a single photomask. The first exposure forms dense gratings using maskless immersion interference lithography. These regular grating patterns are then trimmed in a second exposure with conventional projection lithography. While the highest resolution features are formed with interference imaging, the trimming operation requires significantly lower resolution. We have performed lithography simulations examining a number of representative 32-nm node patterns; both one-dimensional and two-dimensional. The results indicate that 32-nm node lithography requirements can be met using a hybrid optical maskless (HOMA) approach. Trim photomasks can be two to three generations behind the fine features, while the trim projection tools can be one to two generations behind the fine features. This hybrid optical maskless method has many of the benefits of maskless lithography without the severe throughput challenge of currently proposed maskless technologies.
The extension of optical lithography to ever deeper sub-wavelength feature sizes has led to an alarming increase in photo-mask complexity and associated cost. Changes in design philosophy can play a key role in mitigating this trend. We propose the introduction of a new optimization cycle early in the physical design process based on minimizing pattern complexity. We study the use of a pattern complexity metric based on Fourier coding to accomplish such an optimization. The ultimate goal is simplification of resolution enhancement technology (RET) methods required for a given design and the generation of a correspondingly simpler and more cost effective mask set.
A diffraction-grating based demultiplexer is made to have low polarization dependence and high diffraction efficiency properties. The device is made is made of a Si grism working in reflection and having optimised grove profile easily manufactured by standard crystallographic etch of Si surface.
The steady move towards feature sizes ever deeper in the subwavelength regime has necessitated the increased use of aggressive resolution enhancement techniques (RET) in optical lithography. The use of ever more complex RET methods including strong phase shift masks and complex OPC has led to an alarming increase in the cost of photomasks, which cannot be amortized by many types of semiconductor applications. This paper reviews an alternative RET approach, dense template phase shift lithography, that can substantially reduce the cost of optical RET. The use of simple dense grating templates can also eliminate serious problems encountered in subwavelength lithography including optical proximity and spatial frequency effects. We show that, despite additional design rule restrictions and the use of multiple exposures per critical level, this type of lithography approach can make economic sense depending on the number of wafers produced per critical photomask.
Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.
The rise of low-k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only phase shifting mask (PSM) approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1<0.3, thus enabling 90 nm node lithography with high-numerical aperture 248 nm exposure systems. We present the results of experiments, simulations, and analysis designed to explore the trade-offs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.
Image placement errors and their effect on process latitude are a remaining issue in the development of strong phase shift mask technology. In this work, we will review the various causes of image placement error for strong phase shift imaging, including both mask and stepper lens contributions. We will also review various methods of minimizing these image shift errors including the mask fabrication process, stepper lens improvement, and proper design of the lithography process. We will also present experimental results showing how aerial image asymmetry effects can be minimized by the use of an optimized resist process.
The rise of low-k1 optical lithography in IC manufacturing has introduced new questions concerning the physical and practical limits of particular sub-wavelength resoltuion-enhanced imaging approaches. For a given application tradeoffs between mask complexity design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only PSM approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1 < 0.3, thus enabling 90-nm node lithography with high-NA 248 nm exposure systems. We presents the results of experiments, simulations, and analysis designed to explore the tradeoffs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.
The application of strong phase shift masks (PSM's) such as AAPSM and Chromeless using KrF 248-nm lithography is increasingly in demand for production of advanced devices at the 130 nm node and below. Implementation of dual exposure PSM technology is becoming widely accepted as a method to achieve sub-wavelength gate and contact layer resolution for microprocessors, DRAM and thin film heads. This requires a stable and repeatable phase-shift mask process that will perform for the wafer lithographer and is manufacturable using today's leading edge photomask fabrication methods. The focus of this study is the characterization of the photomask quartz etch process. The effect of the photomask's phase depth control and the quartz etch CD control will be examined. A comprehensive mask metrology study will be supplemented by lithography process latitude data, both simulation and experimentally based. The effect of fabricating the photomask quartz trenches using either resist or chrome defined etch masks will also be studied as well as the impact on lithography process latitude. A key goal of this study is the determination of a realistic specification for the quartz etch process required for leading- edge phase-shift photomasks.
We present results looking into the feasibility of 100-nm Node imaging using KrF, 248-nm, exposure technology. This possibility is not currently envisioned by the 1999 ITRS Roadmap which lists 5 possible options for this 2005 Node, not including KrF. We show that double-exposure strong phase- shift, combined with two mask OPC, is capable of correcting the significant proximity effects present for 100-nm Node imaging at these low k1 factors. We also introduce a new PSM Paradigm, dubbed 'GRATEFUL,' that can image aggressive 100-nm Node features without using OPC. This is achieved by utilizing an optimized 'dense-only' imaging approach. The method also allows the re-use of a single PSM for multiple levels and designs, thus addressing the mask cost and turnaround time issues of concern in PSM technology.
Achieving CD control for sub-100 nm processes will be challenging due to the low-k1 regime that optical patterning approaches will be required to work in. New challenges are expected to arise related to new lithography tools, photoresists, reticle types, and in some cases multiple exposures per layer. This work examines the intra-field CD variations for a range of sub-100 nm resist features patterned by chromeless phase-shift 248-nm lithography. One significant advantage of this patterning technique is that the resist CD's are a function of the exposure dose. This provides the ability to examine the CD variations of a range of linewidths in a single experiment without relying on reticle pattern scaling to determine the linewidth printed on the wafer. In addition to exploring CD control vs feature size, we also examine the full-field depth of focus for these features.
One of the issues with using strong phase-shift masks is the transmission asymmetry caused by diffraction effects due to 3D mask topography. The transmission is reduced through the etched portions of the mask and this can result in CD or pitch asymmetries in the printed image. A number of approaches have been suggested to minimize this effect including feature biasing, dual trench and undercut etching. In this work, we investigate the role the resist type can play in minimizing the effects of this aerial image asymmetry. We employ full electromagnetic simulations using PROMAX 2/D and PROLITH 2/D, AIMS simulation, and experiments using chrome-less phase-shift masks as a function of resist type. We conclude that the resist type can play a key role in minimizing the effects of aerial image asymmetry caused by mask topography effects thereby enabling simpler mask fabrication approaches.
This work looks at the application of chromeless phase-shift masks to sub-100 nm gatelength SOI transistor fabrication. The double-exposure technique of Numerical Technologies is extended to the chromeless-edge case. Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates and the second is a binary blockout mask which also patterns the larger gate features. This approach provides considerably enhanced resolution performance compared with alternating aperture while still preserving good process latitudes. The chromeless mask fabrication approach is discussed. A simple, single step dry etch is used with no minimum geometry features, thus simplifying mask fabrication. We employed an 0.6 NA, DUV tool for this work together with commercially available resist and anti-reflection layers. Lithography results for k1 factors down to 0.10 and 0.3 are presented. This corresponds to CDs of 40 nm and 125 nm on our Canon EX-4, 248nm stepper. Excellent pattern transfer into polysilicon was achieved using a high density plasma etch process producing gate features down to 25 nm linewidths. We discuss the application of this method to the fabrication of sub-100 nm gate-length fully-depleted SOI CMOS transistors. We have fabricated SOI CMOS transistors with excellent short channel behavior down to 50 nm physical gate lengths. This method enables the development of deep sub-100 nm gate length CMOS technologies using standard 248- nm exposure sources.
In this work, we explore the application of attenuated phase-shift masks (APSM) to sub-0.18 micrometers logic patterning. Particular attention is paid to proximity effects and the common process corridor between dense and isolated features, a key challenge of logic-level lithography. Using PROLITH simulation, we evaluate APSM performance as a function of mask transmission and stepper illumination mode. The optimum process window was found for weak quadrupole illumination. Experimental results were obtained using a test mask consisting of sub-0.25 micrometers L/S Lbar patterns with various pitch values. We compared the case of a 6 percent APSM mask with weak quadrupole illumination to a standard chrome mask with conventional illumination. Properly optimized, APSM can add significant process latitude for sub-0.18micrometers logic features and may enable 130 nm logic node lithography on standard 248 nm exposure tools.
Strong phase-shift methods such as alternating aperture and chromeless edge are resolution-enhancement techniques that promise to extend optical lithography to the 100-nm regime and possibly below.
The performance of argon fluoride excimer lasers is an important issue in determining the practical feasibility of 193-nm exposure systems. This paper presents a summary of the experience gained at MIT Lincoln Laboratory regarding the long-term performance of 193-nm lasers, used under conditions similar to those expected in production-type lithographic systems.
Laser holographic lithography and selective chemical etching have been used to create GaAs/AlGaAs and InGaAs/GaAs quantum well wires. Strong differences are observed between the photoluminescence spectra from the GaAs and InGaAs quantum wires, with the former being dominated by spatially indirect transitions, and the latter by direct transitions. Detailed time resolved photoluminescence studies show a red shift in photoluminescence energy with increasing time delay after excitation for the indirect transition in the GaAs wires. This is accompanied by a non-exponential decay time which increases from 10 ns to greater than 150 ns as the delay time is increased (in a manner similar to that observed in nipi doping superlattices). The InGaAs wires show no such behavior, with a decay time constant of 320 ps at 1.8 K, independent of time delay after excitation, both indicative of a spatially direct transition.
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