KEYWORDS: Analog electronics, Design for manufacturing, Metals, Resistance, Capacitance, Databases, Back end of line, Tolerancing, Mirrors, Manufacturing
Electrical Design-for-Manufacturability (DFM) checks are developed to quantify layout enhancements and their impact on circuit performance for analog designs. A database containing circuit topologies of analog matched devices is built. Then, connectivity checks scan the schematics for topologies from the database. If a matching topology were detected, the matched devices are mapped to layout for layout matching checks. If layout mismatches are detected, electrical DFM checks are used to quantify the imbalance in terms of parasitic resistance and capacitance. The electrical DFM checks are applied to quantify the impact due to routing, fill, and DFM fixing on three, 22nm analog design blocks. Fill insertion’s contribution to RC change is the greatest followed by routing and DFM fixing, with a maximum change of 7%, 5%, and less than 1%, respectively. Symmetry-aware layout insertions preserve the matching of electrical parameters, showing zero mismatch. All designs pass electrical DFM checks as results are within the expected design tolerances.
A symmetry-aware DFM layout insertion flow for matched circuits is developed for enhancing analog and mixed-signal designs. Pattern capture is used to categorize the matched circuits to unique groups of layout patterns and store them in a pattern database, in which each pattern has an associated group identification, a match location, a region of extent, and a symmetry constraint. Using the stored information in the pattern database, DFM layout insertions are applied to the base pattern and replicated for the symmetric patterns to generate an optimized layout, thus preserving the original symmetry. The impact of the DFM insertions on analog circuit performance was quantified using electronic simulators. The application of symmetry-aware DFM enhancements to analog designs achieves nearly 100% DFM compliance with negligible 0.1-0.2% impact to analog electrical parameters.
KEYWORDS: Design for manufacturing, Analog electronics, Manufacturing, Chemical mechanical planarization, Design for manufacturability, Metals, Extremely high frequency, Yield improvement, Digital electronics, Transceivers
A suite of DFM enablement is enhanced to address the unique needs of analog, RF, and mmWave designs in the custom design flow. The DFM rules and patterns are made stricter beyond baseline requirements, and new DFM rules and patterns are added to further reduce layout-dependent device variability. Auto-fixing in the custom design flow is enhanced to meet these new requirements. New DFM enablement is developed for device matching for differential circuits and sensitive devices. Lastly, novel DFM fill strategies are implemented to reduce the variability of passive devices operating at high frequencies. Using DFM-aware fill, a 2% quality-factor loss for a mmWave inductor operating at 30 GHz is shown to be sufficient for meeting manufacturing planarity requirements.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.