KEYWORDS: Critical dimension metrology, Etching, Semiconducting wafers, Lithography, Process control, Diffractive optical elements, Data centers, Control systems, Data modeling, Process modeling
As die feature sizes continue to decrease, advanced process control has become essential for controlling profile and CD
uniformity across the wafer. Gate CD variation must be suppressed by process optimization of lithography, photoresist
trim, and gate etch in order to achieve the demanding CD control tolerances. Currently, APC is used in the lithography
and etch processes for within wafer (WiW) and wafer-to-wafer (W2W) CD control. APC can make improvements in
process results, but there is still variation that needs to be further reduced. Analysis of the current lithography edge CD
showed that the variation trend transferred to the post-etch edge CD measurement. Additionally, the etch process created
variation in the edge CD independently of the lithography process. It can be challenging to compensate for the variations
in the etch process and such compensations degrade through pitch OPC. Multivariable control of the etch process can
reduce the need for compensations and, consequently, through pitch variation. A DOE was designed and run using the
production etch process as a center reference for the creation of a WiW etch control model. This control model was then
tested with a MATLAB based simulation program that simulates the etch production process sequence and the ability to
target the edge CD. This demonstration shows that through rigorous methodology a multivariate model can be created
for targeting both center CD (W2W) and edge CD (WiW) control, providing an opportunity at etch to reduce
compensation for the etch variations at litho, and to provide the capability at etch to compensate for both litho and etch
uniformity changes by wafer.
Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is
viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated
metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon
gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD
variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical
performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty
of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of
litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that
the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This
paper will examine the current relationship between litho and etch profile control, determine potential limitations for
future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output
(MIMO) modeling.
For several years, integrated scatterometry has held the promise of wafer-level process control. While integrated scatterometry on lithography systems is being used in manufacturing, production implementation on etch systems is just beginning to occur. Because gate patterning is so important to yield, gate linewidth control is viewed by many as the most critical application for integrated scatterometry on etch systems. IBM has implemented integrated scatterometry on its polysilicon gate etch systems to control gate linewidth for its 90 nm node SOI-based microprocessors in its 300 mm manufacturing facility. This paper shows the performance of the scatterometry system and the equipment-based APC system used to control the etch process. Some of the APC methodology is described, as well as sampling strategies, throughput considerations, and scatterometry models. Results reveal that the scatterometry measurements correlate well to CD-SEM measurements before and after etch, and also correlate to electrical measurements. Finally, the improvement in linewidth distribution following the implementation of feedforward and feedback control in full manufacturing is shown.
As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewidth becomes increasingly necessary. This paper shows results from 300 mm wafers with 90 nm technology that were trimmed during the gate formation process on an etch platform. After the process that opened the gate hard mask and stripped the resist, the wafers were measured using both an integrated scatterometer and a stand-alone CD-SEM. The measurements were then used to determine the appropriate amount to be trimmed by the Chemical Oxide Removal (COR) chamber that is also integrated onto the etch system. After the wafers were trimmed and etched, they were again measured on the integrated scatterometer and stand-alone CD-SEM. With the CD-SEM as the Reference Measurement System (RMS), Total Measurement Uncertainty (TMU) analysis was used to optimize the Optical Digital Profilometry (ODP) model, thus facilitating a significant reduction in gate linewidth variation. Because the measurement uncertainty of the scatterometer was reduced to a level approaching or below that of the RMS, an improvement to TMU analysis was developed. This improvement quantifies methods for determining the measurement uncertainty of the RMS under a variety of situations.
New 300mm facilities are decreasing start-up risks by developing new processes on 200mm equipment and transferring the process and manufacturing methods to the 300mm line. 200mm factories have stable processes, equipment and manufacturing methods. Leveraging a common Advanced Process Control (APC) architecture, both semiconductor manufacturers and equipment manufacturers have the ability to extend 200mm equipment capability, and transfer successful APC methods direct. Having a common tool-level APC on both 200mm and 300mm etch equipment, has proven valuable for TEL. Starting with fault detection and process control on 200mm equipment provides for rapid learning and qualification of the APC architecture and interfaces. When transferring the process and manufacturing methods that include APC to 300mm equipment, factories can efficiently ramp up new processes, and focus efforts in areas of high risk that need integrated fault detection. Etch process equipment provides the ultimate challenge due to the lack of physical process models. This requires extensive measurements of equipment and plasma state, followed by the development of empirical models to correlate equipment related state to the process state. The etch process requires chambers to be cleaned and consumable parts replaced, adding a large variable that must be included to make the models robust in high-volume manufacturing. Optimum productivity requires multiplexing 3 or 4 chambers running the same process. Chambers must produce matched process results, while allowing different clean cycles for flexibility of maintenance. Multivariate analysis, relating the equipment and plasma state to the wafer state, is required. A strategy that includes 200mm equipment in parallel with 300mm development supports customer legacy equipment improvements while providing a platform for 300mm APC applications that will extend pas current 200mm tool capability as new processes and manufacturing methods are developed. TEL's Etch APC product allows for equipment integration of real-time data, events, external sensors, and integrated metrology.
Conference Committee Involvement (4)
Data Analysis and Modeling for Patterning Control III
23 February 2006 | San Jose, California, United States
Data Analysis and Modeling for Process Control II
3 March 2005 | San Jose, California, United States
Data Analysis and Modeling for Process Control
26 February 2004 | Santa Clara, California, United States
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