OPC model calibration requires thousands of experimental data points. These are then used to calibrate an OPC model. Today, the majority of these steps are performed manually. Metrology for example involves taking the CD-SEM offline for an operator to program it. Considerable time savings is possible by writing the CD-SEM recipe offline. Experimental data preparation is also often performed manually. Manual review of thousands of data points is a tedious task prone to human errors. Here again, automation can greatly alleviate the engineering effort, reduce cycle-time and improve data quality. Data quality improvement alone has been shown to have a significant benefit to model calibration accuracy and predictability.
In this paper we present an automated solution for the currently engineering effort intensive components of the OPC model calibration flow. The flow we present is integrated inside the OPC environment. We suggest best practices identified through the implementation of an automated flow, and discuss benefits. Our results demonstrate the capability and quantify the benefits which automation brings in human effort, reduced time to accurate model and improved model quality.
An approach to parameter sensitivity methodology for OPC modeling is enhanced, automated, and applied to generate
production-quality models for a 32-nm logic node poly layer. Two parameter sensitivity models are generated and
compared to a baseline model from the same experimental dataset. The three models are thoroughly investigated to
demonstrate that parameter sensitivity can enhance advanced OPC models with essentially no impact on the time
required for model optimization. Results also indicate that parameter sensitivity, if used improperly, can decrease model
quality.
Double patterning technology (DPT) is one of the most practical candidate technologies for 45nm half-pitch or beyond
while conventional single exposure (SE) is still dominant with hyper NA avoiding DPT difficulties such as split-conflict
or overlay issue. However small target dimension with hyper NA and strong illumination causes OPC difficulty and
small latitude of lithography and photomask fabricated with much tight specification are required for SE. Then there
must be double patterning (DP) approach even for SE available resolution.
In this paper DP for SE available resolution is evaluated on lithography performance, pattern decomposition, photomask
fabrication and inspection load.
DP includes pattern pitch doubled of SE, then lithography condition such as mask error enhancement factor (MEEF) is
less impacted and the lower MEEF means less tight specification for photomask fabrication.
By using Synopsys DPT software, there are no software-induced conflicts and stitching is treated to be less impact. And
also this software detects split-conflicts such as triangle or square placement from contact spacing.
For estimating photomask inspection load, programmed defect pattern and circuit pattern on binary mask are prepared.
Smaller MEEF leads less impact to defect printing which is confirmed with AIMS evaluation. As an inspection result,
there are few differences of defect sensitivity for only dense features and also few differences of false defect counts
between SE and DP with less NA. But if higher NA used, DP's inspection sensitivity is able to be lowered Then
inspection load for DP would be lighter than SE.
An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed.
In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.
Single exposure capable systems for the 32nm 1/2 pitch (HP) node may not be ready in time for production. At the
possible NA of 1.35 still using water immersion lithography, one option to generate the required dense pitches is double
patterning. Here a design is printed with two separate exposures and etch steps to increase the pitch. If a 2x increase in
pitch can be achieved through the design split, double patterning could thus theoretically allow using exposure systems
conceived for the 65nm node to print 32nm node designs.
In this paper we focus on the aspect of design splitting and lithography for double patterning the poly layer of 32nm
logic cells using the Synopsys full-chip physical verification and OPC conversion platforms. All 32nm node cells have
been split in an automated fashion to target different aggressiveness towards pitch reduction and polygon cutting. Every
design split has gone through lithography optimization, Optical Proximity Correction (OPC) and Lithography Rule
Checking (LRC) at NA values of 0.93, 1.20, and 1.35. Final comparisons are based on simulations across the process
window. In addition, we have experimentally verified selected single-patterning problem areas on a 1.20 NA exposure
tool (ASML XT:1700Fi at IMEC). With this information, we establish guidelines for double patterning conversions
and present a new design rule for double patterning compliance checking applicable to full-chip scale.
Sub-resolution Assist Features (SRAFs) are powerful tools to enhance the focus margin of drawn patterns. SRAFs are sized so they do not print on the wafer, but the larger the SRAF, the more effective it becomes at enhancing through-focus stability. The size of an SRAF that will image on a wafer is highly dependent upon neighboring patterns and models of SRAF printability are, at present, unreliable.
Conservative SRAF rules have been used to ensure that SRAFs never print on a pattern. More accurate models of SRAF printing should allow SRAF rules to be relaxed, resulting in more effective SRAF placement and broader focus margins.
The process models that are used during Optical Proximity Correction have never been able to reliably predict which SRAFs will print on a pattern. This appears to be due to the fact that OPC process models are generally created using data that does not include subresolution patterns. In addition, the definition of a printing SRAF is not clear, as it can range from a photoresist film left on a wafer to a pattern that is transferred to the substrate during the etch process. This paper will demonstrate a model that identifies SRAFs which appear in photoresist and those which survive the etch step.
Whenever an OPC calibration wafer is exposed, there will be an unavoidable and perhaps non-representative level of
aberration at that part of the exposure field corresponding to where the calibration pattern is written on the mask. In
practice these aberrations values will vary across both the field and from exposure tool to exposure tool. The OPC
engineer is therefore faced with the question of whether the aberrations specific to this part of the reticle field and hence
lens should be taken into account during model fitting. Methodologies have been developed to allow OPC model
calibration when the aerial image is asymmetric either due to the test pattern or the aberrations in the lens that lead to
this. This will be referred to as asymmetry aware model calibration. These methodologies allow asymmetric test
structures to be added to the calibration set to allow greater pattern coverage and therefore allow for a better overall
model fit. Asymmetric calibration structures tend also to be particularly sensitive to asymmetric lens aberrations such as
Coma. The question becomes whether the calibration fit should include asymmetric structures and hence account for
coma, or consider only symmetrical, coma-insensitive structures when doing a model fit.
The paper will investigate, using actual model calibration measurement data the suitability of accounting for model
coma in an actual OPC model calibration.
Emerging resist and etch process technologies for the 45 nm node exhibit new types of
non-optical proximity errors, thus placing new demands on OPC modeling tools. In a
previous paper (SPIE Vol. 6283-75) we had experimentally demonstrated a full resist and
etch model calibration and verified the stability of the model using 45nm node standard
logic cells. The etch model used a novel non-linear etch modeling object in combination
with conventional convolution Kernels. Building upon those results, this paper focuses
on the correction of patterns.
We demonstrate a two-stage optical/resist and etch correction using calibrated models,
including the use of non-linear etch modeling objects. Optical/resist and etch models are
built separately and used sequentially to correct a 45nm logic pattern. Critical areas of
the pattern affected by etch are analyzed and used to verify the correction. Verification
of the correction is obtained through comparison between the simulated contours with the
design intent.
For the 45nm node and beyond, ever smaller CD budgets require tighter control over the entire process, demanding more accuracy from optical proximity correction (OPC). With the industry adoption of model-based over the traditional rules-based approach, OPC has come a long way to improve accuracy. Today, it is time to do the same for another important step in the process: dry etch. Here we demonstrate the accuracy of etch modeling for a 45nm node process. All experiments were conducted at IMEC with an immersion scanner using off axis illumination. Etch was achieved using a non-optimal recipe to exhibit an iso-dense bias effect. SEM data was extracted using a novel tool to automatically remove any experimental noise. Model calibration was performed with ProgenTM using standard and novel etch-sensitive structures. Model accuracy and predictability was verified with comparing modeled 2D contours against CD SEM measurements and images.
Alternating PSM (Alt-PSM) has been recognized as a logical Resolution Enhancement Technique (RET) candidate for the 65nm technology node. One of the key properties this technique has to offer is high Depth of Focus (DOF) and lower Mask Error Enhancement Factor (MEEF). The so-called image imbalance is an Alt-PSM specific property which, if not dealt with correctly, constrains the added DOF. Because of mask topography, intensity differences caused by light scattering become evident between π (180°) and zero degree phase shifters. This causes a line shift that is inversely proportional to the pitch. The traditional solution of applying a fixed trench bias increases the width if the π phase shifter to level out intensities and thus minimize image imbalance. This technique may no longer be sufficient at the 65nm technology node. With the requirement to print even smaller pitches together with a tighter Critical Dimension (CD) budget, intensity imbalance is a larger concern. It may be necessary to apply a pitch dependent or variable trench bias. In this paper, we present a practical OPC modeling approach that accounts for image imbalance. The 2D modeling approach uses boundary layers to represent the 3D effect of light scattering. We demonstrate that with the boundary layer model, it is possible to predict image imbalance caused by mask 3D effects. The model can then be used either to determine the nominal trench bias or can be integrated into the OPC engine to apply a variable trench bias. Results are compared to rigorous Electro Magnetic Field (EMF) simulations and experimental exposures using an ArF scanner, targeting pitches of 130nm and above.
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