Mr. Mark E. Mason Profile

Mark E. Mason

Director of Design Data Integration at Texas Instruments Inc

SPIE Involvement:

Editor | Author

Area of Expertise:

lithography , design for manufacturing

Websites:

Company Website

Publications (23)

Proceedings Article | 19 March 2008 Paper

Paper

Context analysis and validation of lithography induced systematic variations in 65nm designs

Arjun Rajagopal, Anand Rajaram, Raguram Damodaran, Frank Cano, Srinivas Swaminathan, Clive Bittlestone, Mark Terry, Mark Mason, Yajun Ran, Haizhou Chen, Robert Ritchie, Bala Kasthuri, Jac Condella, Philippe Hurat, Nishath Verghese

Proceedings Volume 6925, 69250A (2008) https://doi.org/10.1117/12.778836

KEYWORDS: Silicon, Model-based design, Data modeling, Etching, Scanning electron microscopy, Transistors, Optical proximity correction, Lithography, Critical dimension metrology, Process modeling

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Proceedings Article | 4 March 2008 Paper

Paper

Rules based process window OPC

Sean O'Brien, Robert Soper, Shane Best, Mark Mason

Proceedings Volume 6925, 69251C (2008) https://doi.org/10.1117/12.772790

KEYWORDS: Optical proximity correction, Lithography, Reticles, Transistors, Semiconducting wafers, Model-based design, Data modeling, Process modeling, Failure analysis, Bridges

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Proceedings Article | 27 March 2007 Paper

Paper

Process window and interlayer aware OPC for the 32-nm node

Mark Terry, Gary Zhang, George Lu, Simon Chang, Tom Aton, Robert Soper, Mark Mason, Shane Best, Bill Dostalik, Stefan Hunsche, Jiang Wei Li, Rongchun Zhou, Mu Feng, Jim Burdorf

Proceedings Volume 6520, 65200S (2007) https://doi.org/10.1117/12.714442

KEYWORDS: Optical proximity correction, Metals, Photomasks, Model-based design, SRAF, Tolerancing, Critical dimension metrology, Lithography, Data modeling, Performance modeling

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Proceedings Article | 20 October 2006 Paper

Paper

Finding the needle in the haystack: using full-chip process window analysis to qualify competing SRAF placement strategies for 65 nm

Mark Mason, Shane Best, Gary Zhang, Mark Terry, Robert Soper

Proceedings Volume 6349, 63491X (2006) https://doi.org/10.1117/12.687008

KEYWORDS: SRAF, Optical proximity correction, Resolution enhancement technologies, Optical lithography, Model-based design, Silicon, Lithography, Photomasks, Semiconducting wafers, Picosecond phenomena

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Proceedings Article | 17 March 2006 Paper

Paper

Improving asymmetric printing and low margin using custom illumination for contact hole lithography

Scott Jessen, Mark Terry, Mark Mason, Sean O'Brien, Robert Soper, Willie Yarbrough, Thomas Wolf

Proceedings Volume 6156, 615616 (2006) https://doi.org/10.1117/12.660120

KEYWORDS: SRAF, Printing, Optical proximity correction, Lithographic illumination, Fiber optic illuminators, Lithography, Logic devices, Photomasks, Metals, Logic

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Proceedings Article | 14 March 2006 Paper

Paper

Challenges and solutions for trench lithography beyond 65nm node

Zhijian Lu, Chi-Chien Ho, Mark Mason, Andrew Anderson, Randy Mckee, Ricky Jackson, Cynthia Zhu, Mark Terry

Proceedings Volume 6156, 615617 (2006) https://doi.org/10.1117/12.659242

KEYWORDS: Optical proximity correction, Metals, Model-based design, Design for manufacturing, Lithography, Process modeling, Reticles, Semiconducting wafers, Resolution enhancement technologies, Optimization (mathematics)

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Proceedings Article | 9 November 2005 Paper

Paper

Mask design rules (45 nm): time for standardization

Mark Mason, Christopher Progler, Patrick Martin, Young-Mog Ham, Brian Dillon, Robert Pack, Mitch Heins, John Gookassian, John Garcia, Victor Boksha

Proceedings Volume 5992, 59920D (2005) https://doi.org/10.1117/12.633180

KEYWORDS: Photomasks, Manufacturing, Resolution enhancement technologies, Data modeling, Model-based design, Databases, Inspection, Optical proximity correction, Semiconducting wafers, Design for manufacturing

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Time-to-mask (ttm) has been growing exponentially in the subwavelength era with the increased application of advanced RET's (Resolution Enhancement Technology). Not only are a greater number of design/mask layers impacted but more-and-more layers also have more severe restrictions on critical dimension uniformity (CDU) despite operating at a very low k₁ factors necessitating rigorous but practical tolerancing. Furthermore, designs are also more complex, may be built up from blocks spanning different design styles, and occupy increasingly-large Rayleigh field areas. Given these factors and scales, it's no wonder that the cycle time for verification of a design following RET, is growing however it is doing so exponentially and that this is a critical factor impeding ttm. Until an unambiguously interprable and standard Mask Design Rule (MaskDR) set is created, neither the designer nor the mask supplier can reliably verify manufacturability of the mask for the simple reason that ambiguity and inter-rule conflict are at the source of the problem and that the problem increasingly requires cooperation spanning a large ecosystem of tool, IP, and mask suppliers all needing to essentially speak the same language. Since the 130 nm node, Texas Instruments has enforced a strict set of mask rule checks (MRCs) in their mask data preparation (MDP) flow based on MaskDRs negotiated with their mask suppliers. The purpose of this effort has been to provide an a-priori guarantee that the data shipped to the mask shop can be used to manufacture a mask reliably and with high yield both from a mask standpoint and from the silicon standpoint. As has been reported earlier, mask manufacturing rules are usually determined from assumed or experimentally acquired/validated mask-manufacturing limits. These rules are then applied during RET/MDP data treatment to guide and/or limit pattern correction strategies. With increasing RET and low-k₁ lithography challenges, the importance of MRCs compounds. Furthermore, it will be necessary to comprehend certain MRC restrictions in the design flow as well as in the RET and MDP space. While mask tool manufacturers will need to be able specify tools specifications relevant to the MRCs for a particular mask shop flow, software tool suppliers, such as for RET, need to do so as well with tools which comprehend, check for, and enforce MRCs consistently. IDMs, foundaries, mask shops, EDA companies and tool suppliers will need a common language for the discussion on MaskDRs and MRCs in order to reach unambiguous convergence. Experience at Texas Instruments shows that accurate description, specification, and interpretation of MaskDRs and applying the associated MRCs is critical to a successful advanced mask technology strategy. This paper proposes the creation of a standard MaskDR lexicon. The goal of such a lexicon is the standardization of MaskDRs and their definitions such that interested parties from various mask-related disciplines can discuss, negotiate, specify, test and enforce MaskDRs unambiguously. We further propose that this standard be machine readable and directly usable without the necessity for intermediate interpretations. This lexicon would allow the designers, IDMs, foundaries, mask suppliers, and equipment suppliers to unambiguously negotiate and agree upon mask manufacturability requirements for their particular application.

Proceedings Article | 12 May 2005 Paper

Paper

65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features

Gary Zhang, Mark Terry, Sean O'Brien, Robert Soper, Mark Mason, Won Kim, Changan Wang, Steven Hansen, Jason Lee, Joe Ganeshan

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600409

KEYWORDS: SRAF, Critical dimension metrology, Optical proximity correction, Photomasks, Scanners, Lithographic illumination, Semiconducting wafers, Phase shifts, Lithography, Resolution enhancement technologies

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Proceedings Article | 5 May 2005 Paper

Paper

Design rule considerations for 65-nm node contact using off axis illumination

Scott Jessen, Mark Mason, Sean O'Brien, Mark Terry, Robert Soper, Thomas Wolf

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600005

KEYWORDS: SRAF, Printing, Photomasks, Optical proximity correction, Manufacturing, Lithography, Solids, Logic, Image resolution, Model-based design

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Proceedings Article | 6 December 2004 Paper

Paper

Design, mask, and manufacturability

Mark Ma, Hyesook Hong, Yong Seok Choi, Chi-Chien Ho, Mark Mason, Randy McKee

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569309

KEYWORDS: Photomasks, Manufacturing, Optical proximity correction, Resolution enhancement technologies, Semiconducting wafers, Reticles, Silicon, Design for manufacturing, Scanning electron microscopy, Metals

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Proceedings Article | 3 May 2004 Paper

Paper

The rising cost and complexity of RETs

Mark Mason

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.546794

KEYWORDS: Resolution enhancement technologies, Photomasks, Optical proximity correction, Semiconducting wafers, Lithography, Reticles, Model-based design, Transistors, SRAF, Manufacturing

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Proceedings Article | 10 July 2003 Paper

Paper

OPC on real-world circuitry

Sean O'Brien, Tom Aton, Mark Mason, Carl Vickery, John Randall

Proceedings Volume 5042, (2003) https://doi.org/10.1117/12.485484

KEYWORDS: Optical proximity correction, Lithography, Resolution enhancement technologies, Reticles, SRAF, Silicon, Photomasks, Transistors, Scanning electron microscopy

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Proceedings Article | 14 September 2001 Paper

Paper

Exposure latitude requirements for high yield with photon flux-limited laser sources

Sean O'Brien, Mark Mason

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435780

KEYWORDS: Transistors, Lithography, Semiconductors, Process control, Statistical analysis, Failure analysis, Imaging systems, Transparency, Laser sources, Semiconductor lasers

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Proceedings Article | 22 January 2001 Paper

Paper

Dual-mask model-based proximity correction for high-performance 0.10-um CMOS process

Shane Palmer, Mark Mason, John Randall, Tom Aton, Keeho Kim, Alexander Tritchkov, James Burdorf, Michael Rieger, John Stirniman

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410679

KEYWORDS: Optical proximity correction, Photomasks, Binary data, Data modeling, Etching, Phase shifts, Optical lithography, Databases, Critical dimension metrology, Semiconducting wafers

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Proceedings Article | 5 July 2000 Paper

Paper

Mask error factor impact on the 130-nm node

John Randall, Christopher Baum, Keeho Kim, Mark Mason

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.389049

KEYWORDS: Phase shifts, Binary data, Photomasks, Optical proximity correction, Reticles, Optical lithography, Semiconducting wafers, Printing, Lithography, Cadmium

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Proceedings Article | 5 July 2000 Paper

Paper

Process capability analysis of DUV alternating PSM and DUV attenuated PSM lithography for 100-nm gate fabrication

Keeho Kim, Mark Mason, John Randall, Won Kim

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.388957

KEYWORDS: Photomasks, Lithography, Deep ultraviolet, Critical dimension metrology, Electroluminescence, Optical lithography, Semiconducting wafers, Optical proximity correction, Printing, 193nm lithography

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Proceedings Article | 5 July 2000 Paper

Paper

Manufacturability of 248-nm phase-shift lithography for 100-nm transistors

Mark Mason, John Randall, Keeho Kim

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.388971

KEYWORDS: Photomasks, Reticles, Semiconducting wafers, Binary data, Lithography, Phase shifts, Manufacturing, 193nm lithography, Optical lithography, Transistors

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Proceedings Article | 5 July 2000 Paper

Paper

Influence of film stress on advanced optical reticle distortions

Lowell Siewert, Andrew Mikkelson, Roxann Engelstad, Edward Lovell, Mark Mason, R. Mackay

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.389008

KEYWORDS: Reticles, Etching, Thin films, Photomasks, Metrology, Optical lithography, Optical alignment, Chromium, Chemical elements, Mask making

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Proceedings Article | 25 June 1999 Paper

Paper

Mechanical distortions in advanced optical reticles

Andrew Mikkelson, Roxann Engelstad, Edward Lovell, Theodore Bloomstein, Mark Mason

Proceedings Volume 3676, (1999) https://doi.org/10.1117/12.351143

KEYWORDS: Photomasks, Chromium, Silica, Reticles, Magnesium fluoride, Mask making, Device simulation, Etching, Electron beam lithography, Transmittance

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Proceedings Article | 29 June 1998 Paper

Paper

Cross-sectional critical shape error: a novel methodology for quantifying process simulation accuracy

Mark Mason, Robert Soper

Proceedings Volume 3334, (1998) https://doi.org/10.1117/12.310806

KEYWORDS: Computer simulations, Digital image processing, Edge detection, Image processing, Detection and tracking algorithms, Error analysis, Device simulation, Photomasks, Genetic algorithms, Optical lithography

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Proceedings Article | 7 July 1997 Paper

Paper

Process-specific tuning of lithography simulation tools

Mark Mason, Robert Soper, R. Mark Terry, Chris Mack

Proceedings Volume 3051, (1997) https://doi.org/10.1117/12.275981

KEYWORDS: Lithography, Process modeling, Photoresist processing, Optimization (mathematics)

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Proceedings Article | 13 September 1996 Paper

Paper

Study of integration issues in shallow trench isolation for deep submicron CMOS technologies

Amitava Chatterjee, Mark Mason, K. Joyner, Daty Rogers, Doug Mercer, John Kuehne, A. Esquivel, P. Mei, Suhail Murtaza, Kelly Taylor, Iqbal Ali, S. Nag, Sean O'Brien, S. Ashburn, Ih-Chin Chen

Proceedings Volume 2875, (1996) https://doi.org/10.1117/12.250874

KEYWORDS: Oxides, Etching, Chemical mechanical planarization, CMOS technology, Lithography, Silicon, Photomasks, Scanning electron microscopy, Chemical vapor deposition, Oxidation

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Proceedings Article | 7 June 1996 Paper

Paper

Improved method for the automated determination of E0 for lithography SPC

Mark Mason, Robert Soper, Cesar Garza

Proceedings Volume 2726, (1996) https://doi.org/10.1117/12.240956

KEYWORDS: Semiconducting wafers, Lithography, Process control, Visualization, Photoresist processing, Metrology, Process engineering, Inspection, Optical inspection, Algorithm development

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Showing 5 of 23 publications

Proceedings Volume Editor (3)

SPIE Conference Volume | 18 April 2013

Design for Manufacturability through Design-Process Integration VII

SPIE Conference Volume | 16 April 2012

Design for Manufacturability through Design-Process Integration VI

SPIE Conference Volume | 25 March 2011

Design for Manufacturability through Design-Process Integration V

Conference Committee Involvement (19)

Design-Process-Technology Co-optimization for Manufacturability XII

28 February 2018 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability XI

1 March 2017 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability X

24 February 2016 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability IX

25 February 2015 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability VIII

26 February 2014 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration VII

27 February 2013 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration VI

15 February 2012 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration V

2 March 2011 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration IV

24 February 2010 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration III

26 February 2009 | San Jose, California, United States

Photomask Technology

7 October 2008 | Monterey, California, United States

Design for Manufacturability through Design-Process Integration II

28 February 2008 | San Jose, California, United States

Photomask Technology

18 September 2007 | Monterey, California, United States

Design for Manufacturability through Design-Process Integration

1 March 2007 | San Jose, California, United States

Photomask Technology

19 September 2006 | Monterey, California, United States

Design and Process Integration for Microelectronic Manufacturing IV

23 February 2006 | San Jose, California, United States

Photomask Technology

3 October 2005 | Monterey, California, United States

Design and Process Integration for Microelectronic Manufacturing IV

3 March 2005 | San Jose, California, United States

Design and Process Integration for Microelectronic Manufacturing III

26 February 2004 | Santa Clara, California, United States

Showing 5 of 19 Conference Committees

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