Ms. Margarita Marrero-Martín Profile

Margarita Marrero-Martín

at Univ de Las Palmas de Gran Can

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Publications (6)

Proceedings Article | 28 May 2013 Paper

Rectennas design using DG-MOSFETs

Raúl Rodríguez, B. González, J. García, M. Marrero-Martín, A. Hernández

Proceedings Volume 8764, 876404 (2013) https://doi.org/10.1117/12.2017149

KEYWORDS: Cadmium sulfide, Field effect transistors, Advanced distributed simulations, Transistors, Circuit switching, Cesium, Resistance, Performance modeling, Numerical simulations, Tin

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Proceedings Article | 3 May 2011 Paper

Effect of separation and depth of N+ diffusions in the quality factor and tuning range of PN varactors

M. Marrero-Martín, T. Szydzik, J. García, B. González, A. Hernández

Proceedings Volume 8067, 80670T (2011) https://doi.org/10.1117/12.888663

KEYWORDS: Diffusion, Capacitance, Capacitors, Molybdenum, Microelectronics, Lanthanum, Wireless communications, Tunable filters, Silicon, Transceivers

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Proceedings Article | 10 May 2007 Paper

Influence of the diffusion geometry on PN integrated varactors

J. García, B. González, M. Marrero-Martin, I. Aldea, J. del Pino, A. Hernández

Proceedings Volume 6590, 65901E (2007) https://doi.org/10.1117/12.721999

KEYWORDS: Diffusion, Capacitance, Metals, Polarization, Lanthanum, Silicon, Photography, Calibration, Signal processing, Microelectronics

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Proceedings Article | 30 June 2005 Open Access

Practical considerations for real-time super-resolution implementation techniques over video coding platforms

Gustavo Callico, Sebastian Lopez, Rafael Peset Llopis, Ramanathan Sethuraman, Antonio Nunez, Jose Lopez, Margarita Marrero, Roberto Sarmiento

Proceedings Volume 5837, (2005) https://doi.org/10.1117/12.608322

KEYWORDS: Intelligence systems, Algorithm development, Image processing, Video, Computer programming, Image quality, Super resolution, Image resolution, Motion estimation, Video surveillance

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Proceedings Article | 21 April 2003 Paper

Method of generating trustworthy performance estimations for soft IPs

Margarita Marrero, Pedro Carballo, Antonio Nunez

Proceedings Volume 5117, (2003) https://doi.org/10.1117/12.499074

KEYWORDS: Logic, Transistors, Clocks, System on a chip, Computer aided design, Interference (communication), Semiconducting wafers, Process engineering, Modeling, Instrument modeling

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At 0.25, 0.18 um processes and beyond important process variations occur not only from one fab to another among batches. Moreover as we approach the realm of deep-submicron design, process variations even across a single die are predicted to become a major source of spread. Reduced signal levels, noise margins and timing windows are all contributing to make previously minor variations in geometry and technological parameters a big issue for circuit design. Worse still, new mechanisms appear that cause important variations not only in transistors but also in interconnect. And some of those mechanisms, show greater variation across a single die than across similar structures on different dice from a wafer. Thus the chip designer must expect significant and not necessarily predictable differences between transistors and between interconnect resistances on a single die. Given this scenario widely recognised by process engineers, and given the additional spread built-in in the process of mapping from a soft IP design to a hard IP block, if the designer had the opportunity to know certain performance parameters of the final hard-cores without doing successive synthesis it would lead to an easier and more predictable and accurate integration of the blocks in the system. In this sense, pre-characterised trust-worthy soft-IP blocks would be preferred candidates to select. We have explored ways for quantifying and analysing the synthesis to layout spread so that, instead of modelling the spread in devices and interconnects, we model and quantify at a higher abstraction level the technology mapping process as a whole, for a set of seed designs that will give bounds and guidelines for the behaviour of other designs when they are mapped to the same technology. For that purpose, only the best-, typical-, worst-case and other process variation corners need to be known. The analysis is based in the actual measured spread of reference seed designs as they experience spread when passing from soft to hard designs.

Proceedings Article | 21 April 2003 Paper

Some experiences using system-on-chip buses

Pedro Carballo, Pablo Santos, Margarita Marrero, Antonio Nunez

Proceedings Volume 5117, (2003) https://doi.org/10.1117/12.501356

KEYWORDS: System on a chip, Bridges, Clocks, Virtual colonoscopy, Microcontrollers, Signal processing, Modeling, Data modeling, Control systems, Data communications

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Advances in fabrication and design technologies have contributed to integrate a complete system on a chip. A system-on-chip (SoC) is generally composed of a microprocessor core, on-chip memory and one or more specific coprocessors IPs. One of the major drawbacks of this approach is the differences in the interfaces that each virtual component (VC) of the SoC presents. The idea of a common bus infrastructure allows us to smooth the system integration and has been considered as a design solution for SoC architectures. This paper presents a review of different alternatives for SoC buses and summarizes some experiences of their use. Different alternatives exist for SoC buses. ARM has proposed AMBA (Advanced Microcontroller Bus Architecture) as an open specification that serves as a framework for SoC design. AMBA is a bus architecture multiplayer for high performance SoC designs. AMBA support multi-master configurations where a bus arbiter must be included. AMBA-Lite is a simpler alternative if you are using only one master. IBM uses CoreConnect Bus architecture as a SoC solution for buses. CoreConnect share some similarities with AMBA because both use a multilayer bus to accommodate different speeds in the system: AHB and PLB can be compared. The same situation occurs for APB and OPB. Other alternatives can be found. Wishbone is an Open Bus Specification form opencores.org that tries to solve the problem of IP integration. The idea is to specify a common interface between cores to accelerate the development of virtual components. VSIA has proposed Virtual Component Interface (VCI) as a solution to solve the problem of virtual component integration. VCI specify three types of protocols depending on the level of complexity: Peripheral, Basic and Advanced VCI. The development of the IPs compatible with any of the SoC buses above presented is a complex problem. One solution is the use of wrappers that adapts the interface of the Virtual Component to the protocol supported by the SoC buses. The two main characteristics of these wrappers are that the increased in latency and area would be as low as possible. The second solution is to design the IP with the final environment in mind.

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