KEYWORDS: Modulators, Clocks, Signal to noise ratio, Resistors, Prototyping, Analog electronics, Amplifiers, Feedback signals, Linear filtering, Signal processing
This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The parameters of the analog components of this design are independent of the sampling clock, as long as the clock frequency has to fit only with the length of the external transmission lines. The prototype single-bit modulator was designed for an oversampling ratio of 128. When the modulator is clocked at 53.7MHz achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period and a test tone of -10dBfs is applied, the SNDR is degraded by only 5dB compared to the case without jitter.
This paper proposes an optimization algorithm to reduce the distortion produced in the loop-filter of Continuous-Time Sigma-Delta Modulators. The aim of the algorithm is to find the loop-filter implementation that minimizes distortion at the output of the modulator, by modifying the output swing of every integrator. The algorithm is implemented in Matlab as an evolutive searching. During each step of the searching, the algorithm evaluates the harmonical distortion of a tone when it is applied to the modulator with a certain loop-filter implementation. The output of the algorithm is an optimum linear state-space representation of the loop-filter. This particular state-space representation leads to minimum distortion at the output of the modulator when the loop-filter is implemented with some specific circuitry previously defined. As long as the search is of evolutive type, the solution represents a local minimum only. The algorithm computes a random guess solution as the starting point for the optimization procedure, so that different local minimums may be found by running the algorithm itself several times. The algorithm has been applied to a 4th order 4-bit Continuous-Time Sigma-Delta Modulator as a simulation example.
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