The Cost of Ownership (CoO) for semiconductor processing has been primarily dominated by lithography. In multiple
patterning processes, additional materials and the impact to throughput of multiple patterning passes appear to become
additional major contributors to manufacturing cost as well. We introduce SiOxNy hardmask as a new memorization
layer for multiple patterning that addresses the non-lithographic cost contributor to manufacturing. The optical constants
of the SiOxNy hardmask are matched to those of the photoresist at the imaging wavelength, and that makes it invisible at
the exposure wavelength, enabling lithography directly over the hardmask topography, while at the same time it will be
visible to those wavelengths that are used for alignment and overlay. The SiOxNy hardmask is inserted below the
photoresist which will make the rework and integration schemes much simpler and result in cost savings by replacing
only photoresist layers during multiple patterning processes. Additionally, by eliminating the need for traditional spincast
planarization and the associated tri-layer etch we can improve the critical dimension uniformity (CDU) and reduce
proximity contributions from etch, and their respective etch proximity corrections. In this work, we engineered the
lithographic stack to be compatible with the invisible SiOxNy hardmask. Lithographic process windows, CDU, and
LER/LWR are compared with conventional tri-layer stack and we demonstrate triple patterning memorized into the
SiOxNy hardmask after which patterns are then transferred, at once, into the bottom integrated stack. Finally, major
benefits of using the invisible hardmask on device scaling and patterning challenges are discussed, such as for LE2, LE3,
and trench and cut patterning.
This paper illustrates the increasing importance of line tip printing as measured by the size of the weak line tip zone for
sub-20nm technology. This paper suggests adding line tip printability into sub-20nm lithography performance metric in
addition to the conventional tip-to-tip resolution. This study shows that these two metrics sometimes respond to
lithography conditions inversely. The importance of including line tip printability into technology evaluation is
demonstrated by comparing LELE optical lithography and EUV lithography. Also, line tip printing with EUV
lithography is explored with various illumination conditions and resist developer tones.
The fundamental limits of optical lithography have driven semiconductor processing research to push the envelope.
Double patterning (DP) techniques including litho-etch litho-etch (LELE), litho-litho etch (LLE), and self-aligned
double patterning (SADP) have become standard vernacular for near term semiconductor processing as EUV is not yet
ready for high volume production. The challenge, even with techniques like LLE and SADP, remains that printing small
lines on tight pitches (for LLE) or even small lines on relaxed pitches for mandrel/spacer combinations is not trivial. We
have demonstrated a track-based slimming technique that can produce sub-25 nm resist lines for either SADP or LLE
DP processes. Our work includes results for varying shrink amounts at different target critical dimensions (CD) and for
multiple pitches. We also investigated CD uniformity (CDU) and defectivity. In particular, optimization of the amount
of slimming is critical as it allows for much greater process latitude at the lithography step. In addition to the
lithography work, we have continued the processing for both integration schemes to include oxide deposition and etch
for SADP and through etch performance for DP. We have demonstrated sub 45 nm pitch structures. The wide variety of
process uses, as well as the ability to achieve a large range of shrink amounts shows that track based slimming is a viable
solution to achieve target CD and pitch values for sub 22 nm technology node.
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