KEYWORDS: Machine learning, 3D image reconstruction, Scanning electron microscopy, 3D modeling, Data modeling, Photoresist materials, Performance modeling, Simulations, Monte Carlo methods
In advanced lithography nodes, variations in the sidewall angle and height deformation of photoresists can significantly impact production quality, presenting new challenges for metrology techniques. To address these challenges, we first developed a 3D nano-structure modeling toolkit, T3S, capable of generating a wide range of 3D models with diverse nano-structural features. We then employed a Monte Carlo simulator to generate SEM images of these nano-structures under various primary electron energies and detector settings. Then we analyzed the grayscale profiles of these images. By applying fast Fourier transform, we extracted the frequency domain information from the grayscale profiles of the SEM images, successfully establishing a comprehensive SEM frequency domain database of nano-structures with varying 3D features and SEM operating conditions. Furthermore, we developed a frequency domain-based algorithm to match and predict 3D nano-structural features, such as sidewall angle and height, from unknown SEM images. This database and algorithm enable the rapid and reliable assessment of photoresist shape quality, enhancing process control in advanced lithography nodes.
A prevalent practice in semiconductor fabrication involves the utilization of Graphic Data Systems (GDS) for sampling within the Fab. However, with the reduction in process nodes, the capacity and intricacy of GDS escalate, making efficient and accurate sampling increasingly imperative. The emphasis on sampling varies across diverse application scenarios within the factory. This article delves into the application of machine learning methods to enhance sampling efficiency for Fab applications. It encompasses a spectrum of applications, notably the Photo Resist change project, where machine learning-based sampling techniques are deployed to streamline inspection points. Additionally, the article investigates the potential of machine learning in mask Critical Dimension (CD) performance verification, facilitating real-time monitoring of mask performance through optimized sampling strategies. Moreover, the implementation of SEM down sampling in the defect review process, driven by machine learning, demonstrates the capacity to boost defect hit rates and proficiently identify missing real defects.
Imaging capability of surface plasma based nano-patterning is discussed in this article. The imaging capabilityof 1:1imaging ratio is the basis, which is different with the interference lithography with the frequency multiplicationontheimage plan. In this article, “Superlens” is discussed. The imaging capability evaluation is based on the rigorouselectromagnetic modelling of Finite Element Method. Theoretical analysis and numerical evaluation are given, detailedimpact evaluation of a variety of important parameters to the imaging capability is presented.
Thermal aberration of a projection lens is caused by lens heating and leads to degradation of image quality. Two tasks have been undertaken in this article: first, analysis of the impact of single aberration on imaging quality, and second, use of machine learning to calculate the combination of Zernike aberration coefficients to reduce the influence of aberration on the process window. The impact of aberration on deep ultraviolet (DUV) lithography imaging has been analyzed separately for 16 Zernike terms. The influence of single Zernike coefficient on depth of focus, mask error enhancement factor, and image log slope is comprehensively analyzed by source mask optimization. However, more than one Zernike term is present in the aberration of a real DUV optics. A fully connected neural network (FCNN) model based on machine learning is widely used in the screening of multivariate experiments and can solve the problem of the large number of input variables and the random values of the input data. Its network structure is simple to debug, with fast screening speed and high precision. To make reasonable budget for aberration, an FCNN model is used to find some combinations of Zernike coefficients for different lithographic performance indicators. This implies that the FCNN model has the ability to select a better Zernike combination while each individual Zernike term value falls in the range of −30 to 30 mλ, which plays a guiding role in DUV optics design.
Background: In datasets for hotspot detection in physical verification, data are predominantly composed of non-hotspot samples with only a small percentage of hotspot ones; this leads to the class imbalance problem, which usually hinders the performance of classifiers.
Aim: We aim to enrich datasets by applying a data augmentation technique.
Approach: We propose a data augmentation flow-based generative adversarial network (GAN) to generate high-resolution hotspot samples.
Results: We evaluated our flow with the current state-of-the-art convolutional neural network hotspot classifier by comparison with conventional data augmentation techniques. Experimental results demonstrate that the accuracy improvement of our work can reach 3% at the same false alarm rate and the false alarm rate reduction can reach 5% at the same accuracy.
Conclusions: Our study demonstrates that rational hotspot classification can improve the efficiency of data. It also highlights the potential of GAN to generate complicated layout patterns.
Background: As semiconductor technologies continue to shrink, optical proximity correction may not have enough space to optimize layout due to limitations from adjacent layers. Lithography friendly design (LFD) becomes a powerful tool to detect potential lithography yield killers for fabless side from 14-nm technology node and beyond. Design layout can be modified before tape-out to avoid future rework. However, huge runtime is the bottleneck of LFD.
Aim: Our paper puts forward an innovative layout decomposing algorithm to accelerate LFD at full-chip level.
Approach: The proposed projection-based high coverage fast (PBHCF) LFD layout decomposing algorithm partitions the full-chip layout as a set of unique patterns. The simulation runtime can be reduced by only simulating every unique pattern and corresponding optical interaction range in full chip. The LFD hotspots will be classified, analyzed, and repaired by pattern matching in batches for full-chip layout.
Results: The experiments compare hotspot accuracies and prediction speeds of proposed PBHCF LFD and the most commonly used accelerated algorithm, Smart LFD, for different layouts at chip level for metal 2 layer of 12-nm technology node with pure unidirectional routings. On one hand, the average accuracy of PBHCF LFD can achieve 97.07%, improving 3.4% than Smart LFD on average. On the other hand, PBHCF LFD improves the average prediction speed over regular LFD 19.51%. And the PBHCF LFD is faster than Smart LFD by 5.96%.
Conclusions: PBHCF LFD achieves higher accuracy and less runtime than Smart LFD. The verification experiments conducted on layouts at chip level show the feasibility of the proposed methodology.
With the continuous improvement of chip integration level, resolution enhancement techniques (RET) has become one of the important technologies to promote the continued development of process nodes, such as source mask optimization (SMO), optical proximity correction (OPC) and sub-resolution assist feature (SRAF). Model-based SRAFs are generated by the guidance of the Continuous Transmission Mask (CTM) or SRAF Guidance Map (SGM). During operation, a threshold combined with the ridge is used to extract a suitable location for SRAFs. However, this generation method ignores many details, resulting in the need to constantly adjust SRAFs referring to the SGM/CTM in the subsequent optimization process, which will undoubtedly increase the simulation time. Therefore, we propose a contour line based SRAFs generation method. The extreme value region and the gradient of CTM/SGM will be displayed intuitively, so that more precise positions can be obtained at the initial SRAFs extraction. The SRAFs will be extracted from the extreme value region, and have a distribution similar to the final result. The gradient of the contour line can also be referenced in the following steps to guide the SRAF cleanup. During cleanup process, the SRAFs at high altitude region will have higher priorities to ensure the image quality of main patterns. Another advantage of this method is that when extracting rules from the model-based method, different SRAF priorities can be set according to the contour line and be used in the rules, so as to improve the accuracy of rule-based SRAFs.
Overlay marks contrast plays such a fundamental role for the overlay metrology that it dominants the accuracy control and draws much attention during mark evaluations. However, as the lithography nodes advances and the 3D device stacks accumulate, overlay marks sub-segmentation and opaque hard-masks are widely exploit, both of which can be drawbacks for mark contrast in certain cases. As a result, the overlay mark contrast improvement techniques become a necessity, and attract more research interests. In this paper, we introduced a method to improve the mark contrast by using pixel improvement technique and theoretical reference correlation analysis. Such method can potentially be very effective when measuring overlay marks with extreme low contrast through thick opaque layers.
With the development of process technology nodes, hotspot detection has become a critical process in integrated circuit physical design flow. The machine learning-based method has become a competitive candidate for layout hotspot detector with easy training and high speed. Classic methods usually define hotspot detection as a binary classification problem. However, the designer hopes to further divide the hotspot patterns into a series of levels according to their severity to identify and fix these hotspots. In this paper, we designed a multi-classifier based on the convolutional neural network to realize the detection of various levels of hotspot patterns. Unlike classic cross-entropy loss, we proposed a custom loss function to reduce the difference between false predicted levels and corresponding true levels, reducing the adverse effects caused by misclassified samples. Experimental verification results show that our hotspot detector can correctly classify various hotspots levels and has potential advantages for physical designers to fix hotspots.
As the semiconductor manufacturing critical dimension continues to shrink, the requirement placed on overlay control becomes much more stringent. Due to the fact that the absolute overlay tolerances are approaching 2-3 nm, process induced errors can be a major contribution to the overlay error. For instance, chemical mechanical polishing (CMP) are found to cause 1-3 nm overlay measurement error, which is of the same magnitude to the total overly budget. Because of this, efforts are being made to investigate the mechanism of overlay shift caused by process variations. In this paper, we present a study of the Diffraction based Overlay (DBO) metrology with a model based on the Finite-Difference Time-Domain (FDTD) method on the impact of CMP process to overlay measurement. Measurement error caused by CMP are discussed. Our investigation shows that the impact of the CMP process can cause the +/- diffraction orders to become asymmetric, which will confuse DBO measurement signals. This study has been performed across the visible illumination spectrum and the result of our study will be illustrated.
KEYWORDS: Optical lithography, Immersion lithography, Lithography, Photomasks, Source mask optimization, Manufacturing, Overlay metrology, Data processing, Standards development, Back end of line
In the early stage of technology node definition and process development, design house owns abundant logic patterns resources and is able to offer fab more potential hotspots to do process window check, accelerating design rule qualification, feedback and optimization. A systematic methodology has been put forward to detect potential hotspots categories and modify related design rules with very insufficient process information for fabless side. It is efficient to conduct the study on a small number of patterns which can be treated as the typical of the whole physical design. Hence the physical design can be managed as a library and grouped by specific pattern signature for every layer. Based on the connectivity of source drain layers and local-interconnect layers, via0, under the first metal layer, is adopted litho-etch (LE) x4 on 193i scanner as the lithography solution. The experiment is carried out on the via0 layer. With consideration of minimum size and multiple limitations of other layers in design rule, systematic pattern analysis, fuzzy pattern search for low NILS, high MEEF and large PV bands have been combined to optimize the related design rules.
Via location and metal coverage have direct correlation. Optical proximity correction (OPC) always do selective sizing for metal to offer enough via enclosure, such as extending line end or doing external expansion for related metal edge. Hence via poor landing or metal bridging are both potential hotspots. For 14nm technology node and below, process related weak patterns are highly correlated with via locations and corresponding metal dimensions. A via optimization methodology has been put forward to enhance the robustness of design for physical design in fabless. With the aid of lithography check, the yield killers with high potential relativity with vias will be conducted root cause analysis. This paper describes the main solutions for fabless, including pin location blockage, via shift, via shape change, metal sizing change and so on within design rule check (DRC) constraints. The simulation experiment results prove the effective of these solutions due to related simulated yield killers being eliminated.
Background: As semiconductor technologies continue to shrink, the growth in the number of process variables and combined effects tighten the overall process window, which leads to a more serious yield loss. Yield cannot be totally guaranteed by design rule check and verifications of optical proximity correction, due to complex process variations. The joint effects from unreasonable designs and unstable control of critical dimensions and overlay mainly contribute to the formation of bridging defects in critical interconnect layers. Aim: Our paper puts forward a model to detect the potential bridging region and predicts the corresponding failure probability under a litho-etch-litho-etch process. Approach: The proposed model is based on input error sources from variations of lithography and etch processes. In this scheme, bridging is expected when the minimum space of simulated postetch contours within a specific range is smaller than a user-defined bridging threshold. Gaussian distribution characteristics of line edge roughness (LER) and overlay are considered in the proposed model. Moreover, the proposed model provides meaningful guidelines for bridging prediction with the use of process variation bands. Results: The experiment results indicate consistency and validity of theoretical derivation of the proposed model. The concrete impacts of LER and overlay on the model have been quantitatively analyzed as well. Conclusions: According to the predicted probabilities, the model can early discover potential bridging defects quantitatively by considering the statistical properties of process variations with very few calculations and can give a ranking of failure severity as a decision foundation for design rule optimization.
Block copolymer directed self-assembly (DSA) is a promising technique to print Contact Holes/Vias with polymer blend materials or block copolymers. Polymer blend material is to mix block copolymer and homopolymer. In this paper, the materials we use are polymer blend materials with polystyrene-b-polycarbonate (PS-b-PC) block copolymer and corresponding homopolymer polystyrene. The advantage of polymers is that they do not require complex molecular design and can form cylindrical structures as long as the proportions are right. The polymer can be mixed and used immediately without waiting time. Based on the PS-b-PC which can form a stable lamellar structure, we achieve a controllable cylindrical structure by mixing the two materials and controlling the concentration. After multiple comparison experiments, the phase segregation results of PS-b-PC with PS ratio of 2:1 and 1.5:1 were better, with the diameter about 12.7nm and 14.1nm, and the pitch about 20nm and 22.7nm, respectively.
In the mask manufacturing process, the thickness and sidewall angle of mask are usually determined under the condition of vertical incidence. In fact, the incident angle of light on the mask plane is oblique, especially for the freeform source in source mask optimization (SMO). At this time, the thickness and sidewall angle of mask given by previous methods will not be optimal. This paper presents a method of optimizing mask parameters, which makes the transmittance and phase shift are more optimal for lithography process. In this paper, the influence of variations on mask parameters on lithography process is evaluated by the process window. And the process window corresponding to the optimal mask structure given by our method is larger than that of the original mask structure. The conclusion that the previous mask parameters are not the optimal for lithography process is demonstrated by the simulation results.
With the shrinking of critical dimension, the demand for a process window has reached a new level, which is denoted as the depth of focus at certain exposure latitudes. Therefore, high-quality monitoring and controlling of focus shift are becoming more and more critical. With the purpose of providing an optimal focus monitoring mark, which can be applied in freeform or off-axis illumination with a big sigma and hypernumerical aperture (NA) scheme, a global optimization method combined with the idea of a genetic algorithm is developed. For illustration, two optimal mask structures under quasar and freeform illumination conditions are given by the optimized method. The numerical simulations with the lithography simulator PROLITH are provided to demonstrate the performances of these two structures. In addition, the robustness of these optimized structures is analyzed by considering the phase-shift error in mask manufacturing. The above simulation results verify the effectiveness and validity of the proposed optimization methodology and also show that the mask structure provided by the optimized method has the potential to be an efficient candidate for measuring the defocus of scanners in the immersion lithography with hyper NA.
ASML AH53 and AH74 with higher odd-order diffraction light are the widely used alignment marks in industry to achieve better alignment accuracy by reducing mark damage noise. During lithography alignment process, decent diffraction light power is the basic demand. However, with the use of some high absorption (k is not equal to 0 for detective wavelength) material, it is difficult to detect the light power reflecting from the thick and opaque film stacks with these standard alignment marks. Here we optimized four alignment marks with higher odd-order diffraction power with comparing with AH53 and AH74. One software based on Fourier optical theory is built to quickly calculate the wafer quality (WQ) of different film stacks and different alignment marks. ASML SMASH alignment system can accept customized alignment mark, with new mark type configuration file. In order to demonstrate the effectiveness of new alignment marks, we put the marks on a mask and do the experiments to compare with simulation results. All the experiments results show that new designed alignment marks have larger WQs of odd-order diffraction.
Typically, the printing of contact patterns uses a dark-field (DF) mask in combination with a positive tone resist and positive tone development (PTD) process. PTD, which has a mature process and simulation model, had been widely applied in high-volume manufacturing. For the low aerial image quality of a DF mask in advanced node, PTD is substituted by negative tone development (NTD), which uses a positive tone resist and bright-field mask. Due to the high cost and immature simulation model of NTD process, it is worthwhile to extend PTD to some critical patterns. With the purpose of improving the resist profile and process window (PW) of the contact pattern with a PTD process in advanced node, an optimization method combined with the idea of a genetic algorithm is put forward. For performance of the optimized resist under the conditions of best focus and best dose, an evaluation based on the through pitch square contact patterns with the critical dimension (CD) fixed at 50 nm has been provided. The generalization performance of the optimized resist is also analyzed by a systematic method, which contains the resist profile and PW simulation on the base of through CD and through pitch contact patterns. The above simulation results verify the effectiveness and validity of the proposed optimization method.
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