Litho rule checking (LRC) is now an established component in the mask synthesis flow. Yet the requirements placed on
LRC have grown as process complexity has increased. At 45nm and beyond, new techniques are required to thoroughly
and efficiently evaluate a layout for potential lithographic problems. This paper examines new modeling and checking
techniques which improve the detection of lithographic errors. For more thorough error detection across a wider range
of process points, a process window technique provides checking of potential lithographic errors at nine different process
points. To better detect potential pinches or bridges induced by deep sub-wavelength lithography, a technique which
identifies problems regardless of orientation is used. These techniques provide more thorough checking, both better
accuracy and improved runtime performance across the complete process window.
MEEF (Mask Error Enhancement Factor) has become a critical factor in CD uniformity control since optical lithography process moved to sub-resolution era. A lot of studies have been done by quantifying the impact of the mask CD (Critical Dimension) errors on the wafer CD errors1-2. However, the benefits from those studies were restricted only to small pattern areas of the full-chip data due to long simulation time. As fast turn around time can be achieved for the complicated verifications on very large data by linearly scalable distributed processing technology, model-based lithography verification becomes feasible for various types of applications such as post mask synthesis data sign off for mask tape out in production and lithography process development with full-chip data3,4,5. In this study, we introduced two useful methodologies for the full-chip level verification of mask error impact on wafer lithography patterning process. One methodology is to check MEEF distribution in addition to CD distribution through process window, which can be used for RET/OPC optimization at R&D stage. The other is to check mask error sensitivity on potential pinch and bridge hotspots through lithography process variation, where the outputs can be passed on to Mask CD metrology to add CD measurements on those hotspot locations. Two different OPC data were compared using the two methodologies in this study.
Gate CD (Critical Dimension) control is an important factor in determining semiconductor manufacturing yield. Therefore, its verification prior to mask tape-out is essential to save development time and cost. Not only is fatal-error detection required to ensure high yield, tight CD control in the gate region is equally critical in sub-micron IC manufacturing.
As fast turn around time is achieved for very large data through scalable distributed processing, model-based lithography verification has been utilized for checking the post mask synthesis data quality before mask tape out and RET/OPC process development.
In this paper, we introduce a comprehensive methodology to study and qualify Poly mask layer using a model based lithography verification tool. This flow will include CD checks on both gate-width and gate- length dimensions. Gate CD distribution plots on the poly layer will be done across a complete range of target CDs in order to investigate wafer CD uniformity errors on full-chip level under various process conditions. In addition, the traditional edge-placement detection will be discussed and compared to absolute CD verification process.
Model based full-chip lithography verification has been proven as a mask sign off solution to prevent patterning failures caused by design/OPC (Optical Proximity Correction) before mask data tape out. Furthermore, as the fast turn around time is achieved through scalable distributed processing for very large data after mask synthesis conversion such as assist feature and OPC, model-based full-chip verification can take advantages of RET (Resolution Enhancement Technique)/OPC recipe development. In previous studies, we introduced the full-chip verification methodologies for mask sign off flow in production and for RET/OPC optimization flow in process development stage for sub-wavelength lithography processes in general.
In this paper, we demonstrated the layer-specific verifications for critical layers for 65nm lithography process development. For poly layer, we performed various types of checks such as fatal pinch/bridge hotspots, CD variations, line-end/space-end errors, assist feature printability, MMEF (Mask Error Enhancement Factor) and geometrical (Mask Rule/structural) checks considering the mask manufacturing constraints. We compared hyper NA (Numerical Aperture)illumination using immersion lithography with the double expose alternating PSM (Phase Shift Mask) lithography. For metal layer, various full-process window coverage verification methodologies were discussed.
Contact and via layers are becoming more critical than before from lithography point of view due to the fact that the contact and via sizes for advanced devices are falling into deep sub-wavelength ranges. In this study, we will demonstrate several different methodologies for contact and via CD variation check and contact/metal overlay checks on the post-opc data using a model based verification software platform. Our study reveals that the full chip verification for the contact and via layers is necessary
achievable to guarantee the mask data quality and to prevent catastrophic pattern errors resulting from improper OPC corrections. Good scalability of the software methodology and platform makes it possible to do the full chip verification with reasonable turn around
time.
Resolution enhancement techniques and OPC(Optical Proximity Correction) have been developed with empirical data points from general test patterns and some actual patterns extracted from full-chip design. Lithography simulation tools have been used for intensive process simulation to optimize RET solutions using sample patterns to cover whole full-chip patterns. However, as design complexity increases and mask manufacturing rules restrict process proximity correction coverage, post-RET/OPC data can generate fatal patterning failures at locations where the process window is marginal. Therefore, it is necessary to identify those patterns from full-chip layout to choose proper RET/OPC solutions. Previously, it was proven that model based full-chip verification tool is useful to capture potential fatal patterning failures before mask tape-out sign-off for sub-wavelength lithography processes. [1] In this paper, we extended the full-chip verification methodology to quantitative RET/OPC development using database error analysis. First, using GDS data containing design intent only and a single 90nm lithography process calibrated model, we performed full-chip verification for linearly scaled designs through 130nm, 90nm and 65nm node to take OPC directions. Second, a standard OPC recipe was applied for each design node followed by verification. And then, potential pattern failures at 65nm node were analyzed through lithography process window. Finally, RET/OPC solution was discussed for 65nm design.
For the 90nm-lithography node, understanding the impact of various reticle pinhole defects on wafer printability is essential to optimize wafer yield and to create the best quality reticle defect specification. In this study, a new programmed pinhole test reticle was designed by UMC, TCE and KLA-Tencor based on UMC's process requirements for its 193nm lithography. The reticle was manufactured and inspected on KLA-Tencor's high-resolution reticle inspection system in die to database mode by TCE. The reticle was then printed on a wafer by UMC to characterize the printability impact of programmed pinhole defects. The programmed pinhole test reticle, "193PTM", consists of two IC background patterns - poly gate and contact with programmed pinholes at various locations. The pinhole size ranges from 20nm to 75nm in 5nm increments on the wafer. By comparing the high-resolution pattern inspection results to the wafer print data, we have established the correlation and the appropriate mask specifications based on wafer application guidelines.
Contacts and VIAs are features whose integrity are very susceptible to reticle CD defects or in general, to defects that produce a change of total energy (flux) projected through the reticle. As lithography is extended beyond the 130nm node, the problem becomes more critical. Detecting and analyzing photomask critical dimension (CD) errors and semitransparent defects is vital for qualifying reticles to enable high IC wafer yield for the 90nm node. The current state of the art inspection methods are unable to meet the industry requirements for contact and via features. Using the TeraStarTM pattern inspection system's image computer platform, a new algorithm, TeraFluxTM, has been implemented and tested for the inspection of small 'closed' features. The algorithm compares the transmitted energy flux difference between a test contact (or a group of contacts) and a reference image for small closed features, such as, contacts, trenches, and cells on chrome and half-tone reticles. The algorithm is applicable to both clear and dark field reticles. Sensitivity characterization tests show that the new algorithm provides CD error detection to 6% energy flux variation with low false defect counts. We performed experiments to correlate the sensitivity performance of the new algorithm with wafer printability results. The results will be presented together with results of inspections results of programmed defect plates and production reticles.
Sub-wavelength lithography used for 9Onm node devices requires new approaches to both lithography processes and reticle design. Reticle complexity has increased as OPC and Phase Shift techniques are used to improve lithography process windows at smaller design rules. This paper will discuss the results of algorithms developed for specific layers to extend the TeraStar reticle inspection tool to 9Onm reticle research and development applications. Lithographically challenging layers have been the focus of the algorithm development programs, specifically gate layers and contact/via layers. Alternating phase shift masks are gaining importance as a reticle enhancement technique to meet the ITRS Litho Roadmap 9Onm node line widths. A new class of TeraPhase algorithms has been developed for alternating phase shift mask inspection with a focus on gate layers. Die-to-die and die-to-database inspection results will be presented for alternating phase shift programmed defect test plates and production gate layers. Contact and via layer reticles are some of the most difficult layers for CD and lithography process window control. A new family of TeraFlux algorithms has been developed based on flux energy differences between contacts to significantly improve sensitivity to lithographically significant CD errors. Die-to-die and die-to-database inspection results will be presented for contact programmed defect test plates and production contact and via layers. Comparisons of the newly developed algorithms will be made to previous generation inspection capability.
With growing implementation of low k1 lithography on DUV scanners for wafer production, detecting and analyzing photomask critical dimension (CD) errors and semitransparent defects is vital for qualifying photomasks to enable high IC wafer yields for 130nm and 100nm nodes. Using the TeraStar pattern inspection system's image computer platform, a new die-to-database algorithm, TeraFlux, has been implemented and tested for the inspection of small "closed" features. The algorithm is run in die-to-database mode comparing the energy flux difference between reticle and the database reference for small closed features, such as, contacts, trenches, and cells on chrome and half-tone reticles. The algorithm is applicable to both clear and dark field reticles. Tests show the new algorithm provides CD error detection to 6% energy flux variation with low false defect counts.
We have characterized the sensitivity and false defect performance of the die-to-database energy flux algorithm with production masks and programmed defect test masks. A sampling of inspection results will be presented. Wafer printability results using the programmed defects on a programmed defect test reticle will be presented and compared to the inspection defect sensitivity results.
This paper discusses the challenges to alternating phase shift mask defect inspection and new approaches for phase defect detection using multiple illumination methods in conjunction with defect detection algorithm modifications. Die-to-die inspection algorithms were developed for the KLA-Tencor 365UV-HR (APS algorithm) and TeraStar SLF27 (TeraPhase algorithm) inspection systems based upon the use of simultaneous transmitted and reflected light signals. The development of an AltPSM programmed test vehicle is described and defect sensitivity characterization results from programmed phase defect reticles are presented. A comparison of the two approaches used for the different inspection systems is discussed. A comparison of TeraPhase to transmitted light only results from a programmed phase defect test mask shows improved phase defect detection results.
Alternating phase shift masks (altPSM) are gaining importance as a reticle enhancement technique to meet the ITRS Litho Roadmap sub-130 nm node line widths. AltPSM fabrication usually involves etching of the quartz substrate in order to form the phase shift structures. Defects can arise during the quartz-etching step from imperfections in the resist image thereby causing various forms of phase shifting defects on the reticle. These reticle phase shift defects can result in printable defects on the wafer. In order to prevent wafer yield loss from occurring, it is necessary to detect and repair the reticle defects. A die-to-die inspection algorithm using simultaneous transmitted and reflected light signals was developed for the KLA-Tencor TeraStar SLF27 inspection system. The algorithm processes the transmitted and reflected light signals in parallel to detect both phase and chrome defects at high speed. One of the several challenges in the use of reflected light for pattern defect detection on alternating phase shift masks is to ignore lithographically insignificant mask process artifacts such as bright chrome 'halos' which may exhibit significant differences between adjacent die. This paper discusses the inspection challenges of alternating phase shift masks. Defect sensitivity characterization results from programmed phase defect reticles are presented.
Sizing of programmed defects on optical proximity correction (OPC) feature sis addressed using high resolution scanning electron microscope (SEM) images and image analysis techniques. A comparison and analysis of different sizing methods is made. This paper addresses the issues of OPC defect definition and discusses the experimental measurement results obtained by SEM in combination with image analysis techniques.
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