Proceedings Article | 9 April 2024
Toshihiro Ifuku, Masami Yonekawa, Kazuki Nakagawa, Kazuhiro Sato, Tomohiro Saito, Sentaro Aihara, Toshiki Ito, Kiyohito Yamamoto, Mitsuru Hiura, Keita Sakai, Yukio Takabayashi
KEYWORDS: Nanoimprint lithography, Semiconducting wafers, Overlay metrology, Optical lithography, Lithography, Molybdenum, Ecosystems, Printing, Metrology, Particles
Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15 to 20% of the minimum half pitch. For 14nm, this means 2.1 to 2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL, an attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. To establish a new lithographic production solution requires the support of an ecosystem in order to enable seamless insertion of the technology. In this paper, review the current performance of Canon’s and then move on to discuss a variety of ecosystem technologies including drop pattern generation, NIL process simulation, virtual metrology support and pattern transfer techniques that can be applied to different markets. Finally, we touch on other applications that can be addressed with NIL and show some processing examples.
