Andrew Walker, Stuart Fancey, M. Forbes, Gerald Buller, Mohammad Taghizadeh, Marc Desmulliez, Julian Dines, C. Stanley, G. Pennelli, Andrew Boyd, J. Pearson, Paul Horan, Declan Byrne, John Hegarty, Sven Eitel, Hans-Peter Gauggel, Karlheinz Gulden, A. Gauthier, P. Benabes, J. Gutzwiller, Michel Goetz
The physical limit on electronic data communication rates between silicon chips is projected to be of the order of Tbit/s over cm-scale connections. The semiconductor industry predicts that this level of i/o is likely to be required in the near future. Free-space optical connections to silicon VLSI are potentially able to offer much higher data-rates than electrical interconnects and are promising for future high-performance electronic systems. We have assembled the components of an optoelectronic 15 Gbit/s crossbar switch designed to include, internally, an optical data rate to a hybrid InGaAs/silicon chip in the Tbit/s regime. Input to the demonstrator is by an 8 X 8 VCSEL array operating at 250 Mbit/s channel, and these 64 channels are fanned out 8 X 8 times to give the high data rate onto the hybrid chip. This chip includes an array of 4096 InGaAs-based detectors flip chip bonded to silicon CMOS. The custom- designed CMOS performs packet routing under the control of an optical clock and the routed signals are output via differential modulator pairs, interlaced between the detectors on the InGaAs chip.
The performance of a novel acylate-based thermally stable photo-polymer is presented. Rapid direct writing of the guides and other structures is realized using a high-power 325 nm He:Cd laser. The loss is measured by cut-back to be less than 0.17 dB/cm at 850 nm and less than 0.5 dB/cm at 1310 nm. This material and writing system is used to make 50 micrometers square core cladded guides and compliant bumps for device attachment, and 45 degree(s) TIR mirrors for out of plane coupling.
The increasingly high performance of electronic processors will place a burden on data communications in future systems. High speed and dense interconnections will be needed at various levels of a system hierarchy: among gates on a chip; among chips on a multi-chip module (MCM); among chips or MCMs on a board, and among boards via a backplane.
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