The yield of the deep sub-micron semiconductor is secured by the process capability as well as the yield-friendly design capability. Yield-friendly design capabilities can be equipped with conventional Design for Manufacturability (DFM) that avoids already known defective layouts in design. Previously known defects can be defined as various rules and avoided in design, but defects that may occur at new technology nodes are difficult to avoid in advance. Indiscreetly defect-avoidance designs cause turn TAT increases and Power/Performance/Area (PPA) overheads in the design, which can ultimately lead to increased design costs and poor design competitiveness. The first step of this study is to predict potential risks and to specify major factor of risks that may occur at new process nodes with new DFM solutions developed using Machine Learning (ML) techniques. The second step is to secure early yield through avoidance design to prevent predicted defects and direct mask modification to improve defects. In this study, we present not only the introduction of new ML-based DFM solutions, but also the effect of predicting and improving defects through the application cases of real products.
Process and reliability risks have become critically important during mass production at advanced technology nodes even with Extreme Ultraviolet Lithography (EUV) illumination. In this work, we propose a design-for-manufacturability solution using a set of new rules to detect high risk design layout patterns. The proposed methods improve design margins while avoiding area overhead and complex design restrictions. In addition, the proposed method introduces an in-design pattern replacement with automatically generated fixing hints to improve all matched locations with identified patterns.
Due to limited availability of DRC clean patterns during the process and RET recipe development, OPC recipes are not tested with high pattern coverage. Various kinds of pattern can help OPC engineer to detect sensitive patterns to lithographic effects. Random pattern generation is needed to secure robust OPC recipe. However, simple random patterns without considering real product layout style can’t cover patterning hotspot in production levels. It is not effective to use them for OPC optimization thus it is important to generate random patterns similar to real product patterns. This paper presents a strategy for generating random patterns based on design architecture information and preventing hotspot in early process development stage through a tool called Layout Schema Generator (LSG). Using LSG, we generate standard cell based on random patterns reflecting real design cell structure – fin pitch, gate pitch and cell height. The output standard cells from LSG are applied to an analysis methodology to assess their hotspot severity by assigning a score according to their optical image parameters - NILS, MEEF, %PV band and thus potential hotspots can be defined by determining their ranking. This flow is demonstrated on Samsung 7nm technology optimizing OPC recipe and early enough in the process avoiding using problematic patterns.
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