A. Marcia Almanza-Workman, Albert Jeans, Steve Braymen, Richard Elder, Robert Garcia, Alejandro de la Fuente Vornbrock, Jason Hauschildt, Edward Holland, Warren Jackson, Mehrban Jam, Frank Jeffrey, Kelly Junge, Han-Jun Kim, Ohseung Kwon, Don Larson, Hao Luo, John Maltabes, Ping Mei, Craig Perlov, Mark Smith, Dan Stieler, Carl Taussig, Steve Trovinger, Lihua Zhao
Good surface quality of plastic substrates is essential to reduce pixel defects during roll-to-roll fabrication of flexible
display active matrix backplanes. Standard polyimide substrates have a high density of "bumps" from fillers and belt
marks and other defects from dust and surface scratching. Some of these defects could be the source of shunts in
dielectrics. The gate dielectric must prevent shorts between the source/drain and the gate in the transistors, resist shorts in
the hold capacitor and stop shorts in the data/gate line crossovers in active matrix backplanes fabricated by self-aligned
imprint lithography (SAIL) roll-to-roll processes. Otherwise data and gate lines will become shorted creating line or
pixel defects. In this paper, we discuss the development of a proprietary UV curable planarization material that can be
coated by roll-to-roll processes. This material was engineered to have low shrinkage, excellent adhesion to polyimide,
high dry etch resistance, and great chemical and thermal stability. Results from PECVD deposition of an amorphous
silicon stack on the planarized polyimide and compatibility with roll-to-roll processes to fabricate active matrix
backplanes are also discussed. The effect of the planarization on defects in the stack, shunts in the dielectric and
curvature of finished arrays will also be described.
Albert Jeans, Marcia Almanza-Workman, Robert Cobene, Richard Elder, Robert Garcia, Fernando Gomez-Pancorbo, Warren Jackson, Mehrban Jam, Han-Jun Kim, Ohseung Kwon, Hao Luo, John Maltabes, Ping Mei, Craig Perlov, Mark Smith, Carl Taussig, Frank Jeffrey, Steve Braymen, Jason Hauschildt, Kelly Junge, Don Larson, Dan Stieler
A solution to the problems of roll-to-roll lithography on flexible substrates is presented. We have developed a roll-toroll
imprint lithography technique to fabricate active matrix transistor backplanes on flexible webs of polyimide that
have a blanket material stack of metals, dielectrics, and semiconductors. Imprint lithography produces a multi-level 3-
dimensional mask that is then successively etched to pattern the underlying layers into the desired structures. This
process, Self-Aligned Imprint Lithography (SAIL), solves the
layer-to-layer alignment problem because all masking levels are created with one imprint step. The processes and equipment required for complete roll-to-roll SAIL fabrication will be described. Emphasis will be placed on the advances in the roll-to-roll imprint process which have enabled us to produce working transistor arrays.
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and
Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise
overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the
pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field
and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of
multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it
is critical to address the infrastructure associated with the fabrication of templates.
For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x
templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial
variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing
these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing
technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using
Samsung's current flash memory production device design. The fabrication of the template is discussed and the
resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting
results are described in terms of CD uniformity, etch results, and overlay.
Imprint lithography has been shown to be an effective method for the replication of nanometer-scale
structures from an imprint mask (template) or mold. Step and Flash Imprint Lithography (S-FIL®) is unique in its
ability to address both resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has
been demonstrated. Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint
lithography as a Next Generation Lithography (NGL) solution for IC production. During the S-FIL process, a
transferable image, an imprint, is produced by mechanically molding a liquid UV-curable resist on a wafer.
Acceptance of imprint lithography for CMOS manufacturing will require demonstration that it can attain defect levels
commensurate with the requirements of cost-effective device production. This report summarizes the result of defect
inspections of wafers patterned using S-FIL. Wafer inspections were performed with KLA Tencor- 2132 (KT-2132)
and KLA Tencor eS23 (KT-eS32) automated patterned wafer inspection tools. Imprint specific defectivity was shown
to be ≤3 cm-2 with some wafers having defectivity of less than 1 cm-2 and many fields having 0 imprint specific
defects, as measured with the KT-2132. KT eS32 inspection of 32 nm half pitch features indicated that the random
defectivity resulting from the imprint process was low.
Imprint lithography has been shown to be an effective method for the replication of nanometer-scale
structures from a template mold. Step and Flash Imprint Lithography (S-FIL®) is unique in its ability to address both
resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has been demonstrated.
Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint lithography as Next
Generation Lithography (NGL) solution for IC production. During the S-FIL process, a transferable image, an imprint,
is produced by mechanically molding a liquid UV-curable resist on a wafer. The novelty of this process immediately
raises questions about the overall defectivity level of S-FIL. Acceptance of imprint lithography for CMOS
manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective
device production. This report specifically focuses on this challenge and presents the current status of defect
reduction in S-FIL technology and will summarize the result of defect inspections of wafers patterned using S-FIL.
Wafer inspections were performed with a KLA Tencor- 2132 (KT-2132) automated patterned wafer inspection tool.
Recent results show wafer defectivity to be less 5 cm-2. Mask fabrication and inspection techniques used to obtain low
defect template will be described. The templates used to imprint wafers for this study were designed specifically to
facilitate automated defect inspection and were made by employing CMOS industry standard materials and exposure
tools. A KT-576 tool was used for template defect inspection.
Researchers have demonstrated that imprint lithography techniques have remarkable replication resolution and can pattern sub-5nm structures. However, a fully capable lithography approach needs to address several challenges in order to be useful in manufacturing. For successful manufacturing insertion of Step and Flash Imprint Lithography (S-FILTM) into a broad set of applications such as photonics, magnetic storage, and integrated circuits (ICs), the following practical process related challenges need to be addressed: (i) Printing sub-50nm structures with non-uniform pattern densities: (ii) Precise alignment and overlay with the ability to mix-and-match with photolithography; (iii) Availability of 1X templates; (iv) Achieving appropriate throughput for acceptable cost of ownership; and (v) Minimizing template and imprint process-induced defects to allow acceptable process yields. The last challenge - the ability to achieve low defect densities - is desirable for all applications. However, it is one of the biggest challenges for S-FIL to be accepted in IC fabrication. This article specifically focuses on this last challenge and presents the current status of defect reduction in S-FIL technology.
The article starts out by providing a brief background of S-FIL technology, and by including a discussion of the overall status of S-FIL technology in Section 1. Next, an overview of the experiments performed including the defect inspection approaches used is provided in Section 2. Section 3 introduces the classes of defects that are relevant to the S-FIL process. It also provides recent defect data for each of these classes. Section 4 presents defect data gathered over the last three years and provides defect reduction trends over this period. Section 5 discusses the topic of template lifetime. Finally Section 6 provides some concluding remarks. The defect data presented here is based on a large number of short-loop experiments based on optical inspection of templates and wafers; these data are complemented by a modest number of high resolution e-beam inspections to provide insight into S-FIL specific defects at leading edge line widths.
KEYWORDS: Photomasks, Ions, Etching, Ion beams, Lithography, Molecules, Electron beams, Image resolution, Scanning electron microscopy, Signal to noise ratio
The efficacy of currently available repair techniques has been assessed for a wide variety of defect types encountered on advanced lithographic masks. Focused ion beam (FIB) with gas-assisted etching and deposition, electron beam induced chemical processing (EBIC), and atomic force microscope based nano-machining (RAVE) were among the different methodologies evaluated. Various types of optical phase-shifting masks for the 45nm lithographic node, as well as nano-imprint lithography (NIL) templates, were used as test vehicles. Defect imaging resolution, spatial process confinement, repair edge placement, end-pointing control, sample damage (undesired changes in topographic or optical properties), and future extendibility served as the primary metrics for gauging repair performance. The primary aim of this study was to provide a single "snapshot" in time of the current development status of each tool for the context of 45nm node mask repair specifications and by no means were there any expectations for a final solution to already be commercially available. However, the results obtained from these tests should provide useful feedback and information to help improve the learning cycle for the development of 45nm lithographic node mask repair systems.
Recent interest and inclusion to the ITRS roadmap for the investigation of NIL (Nano Imprint Lithography) has brought back to life 1X mask making. Not only does NIL require 1X pattering, it also requires physical contact with the patterning media, which, for obvious reasons, raises defectivity concerns. NIL is capable of reproducing features in the 50-10nm range, and possibly below, creating extensive manufacturing challenges for NIL tooling. KLA-Tencor has partnered with Molecular Imprints Inc. of Austin, Texas to study the eventual implementation and commercialization of NIL, especially as it pertains to the IC segment of the market. Photronics Labs Inc. is also involved in the NIL effort by developing and understanding the issues required for successfully producing commercially available tooling for this new lithography technique. Much of this work supported by NIST project #00-00-5853.
The improvement in effective resolution of photo masks and templates is demonstrated by reducing pattern collapse through the use of surface conditioners. The masks were coated with a chemically amplified negative e-beam resist, FEN270, and exposed on a 50keV e-beam system. The factors investigated in this experiment included two surface conditioner (SC) formulations, SC concentration, exposure dose, post bake temperature, and resist thickness. A test pattern was designed to pinpoint the onset of resist collapse. Line sizes from 40nm to 130nm were tested with different line spacing to exert varying amounts of capillary forces on the resist walls. Surface conditioners were manually dispensed prior to the final spin dry step. The results were compared to masks processed in the same manner but with DI water as a control. OptiPattern 50% concentration surface conditioner showed the most significant resolution improvement with approximately 23nm increase from the baseline. Some adverse swelling effects were observed with some formulations.
Imprint lithography has been proposed as a low cost method for next generation lithography for the manufacturing of semiconductors for the 45nm node and below, as costs for traditional optical lithography, and EUV lithography escalate to new levels that may prohibit new semiconductor devices from ever coming to market. While this was the widely proposed use of this technology, a whole host of new areas can take advantage of this lower cost manufacturing technology also. The template enables imprinting all these devices. Template manufacturing and development is currently done along side of state of the art reticle manufacturing. While the dimensions of the 1X templates is significantly smaller than what is needed for optical lithography templates, the dimensions are on the same order as the optical assist features, scatter bars and serifs used today. We will show current capability of 1X templates for imprint applications that are available commercially today, for semiconductor and nanofabrication applications. The advantages on the wafer side for the adoption of imprint lithography is the simplification of processing, reduced capital costs and process control when integrated in the wafer fab. The adoption of imprint reduces the barrier of entry to state of the art resolution for many older existing fabs that cannot spend upwards of 30 million dollars on an immersion I-line cluster. In this paper we will explore not only the technical aspects of imprint lithography, but also the economic impact as well.
Imprint lithography has been proposed as a low cost method for next generation lithography for the manufacturing of semiconductors for the 45nm node and below, as costs for traditional optical lithography, and EUV lithography escalate to new levels that may prohibit new semiconductor devices from ever coming to market. While this was the widely proposed use of this technology, a whole host of new areas can take advantage of this lower cost manufacturing technology. MEMS devices that can be scaled to smaller dimensions, construction of nano-optical devices for OLED applications, biosensors, light dispersion gratings and many other types of devices in need of nanometer scale fabrication. The template enables imprinting all these devices. Template manufacturing and development is currently done along side of state of the art reticle manufacturing. While the dimensions of the 1X templates is significantly smaller than what is needed for optical lithography templates, the dimensions are on the same order as the optical assist features, scatter bars and serifs used today. We will show current capability of 1X templates for imprint applications that are available commercially today, for semiconductor and nanofabrication applications.
Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/-9nm. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as seen with contacts. This study included the use of multiple, high transmission, 193nm attenuated phase shifting mask varieties to meet the difficult challenges of 65nm contact and trench lithography. Numerous illumination schemes, mask biasing, optical proximity correction (OPC), mask manufacturing techniques, and mask blank substrate materials were investigated. The analysis criteria included depth of focus, exposure latitude and MEF through pitch, reticle inspection, reticle manufacturability, and cost of ownership. The investigation determined that certain high transmission reticle schemes are strong contenders for 65nm generation contact and trench patterning. However, a number of strong interactions between illumination, OPC, and reticle manufacturing issues need to be considered.
Semiconductor manufacturers are increasingly focusing on contact and via layers as the most difficult lithography pattern. Focus and exposure latitude, MEF, as well as iso-dense bias are challenges for contact patterning. This situation is only expected to worsen for the 65nm device generation where the 2001 SIA roadmap update lists the contact size as 90-100nm in 2004-2005. Thus, new contact pattern techniques with novel manufacturability are required. One possible avenue to meet these stringent process control requirements is the use of tri-tone high transmission attenuated phase shifting masks (tri-tone AttPSM) for the 65nm generation.
Multilayered SiN/TiN (9%-18%) EAPSM materials to manufacture advanced reticles were used in this investigation. Extensive study during the photomask processing (Front End and Back End) to access any issues related to the making of High %T tri-tone product types was performed.
Finally, the 2 prototype reticles were evaluated on a 193nm scanner (0.75NA) with various illumination settings to generate imaging to support the 65nm node technology generation.
Alternating aperture phase shifting mask (AAPSM) technology is finding increased use in the patterning of critical layers due to the enhanced resolution and decreased linewidth variation characteristic of this technique. The potential advantages of AAPSM processes must be weighed against the increased complexity of reticle layout, higher reticle cost, and heightened sensitivity to parameters such as lens aberration. This work details the effect of shifter trench depth on patterning performance for the 100nm node. Data was collected at an exposure wavelength of 193nm using reticles built with deliberate errors in shifter trench depth. Differences in patterning performance observed as a result of these variations are compared with the impact predicted from modeling.
Repair and printability of 193nm alternating aperture phase shift masks have been studied in detail in an effort to understand the overall production capability of these masks for wafer production at the 100nm node and below.
SEMICONDUCTOR300 was the first pilot-production facility for 300mm wafers in the world. The company, a joint venture between Motorola, Inc. and Infineon Technologies started in early 1998 to test and compare process, metrology and probe equipment, develop robust processes, and manufacture products using a 300mm wafer tool set. The lithography tools included I-line steppers, an I-line scanner, a DUV stepper, and DUV scanners. All of these exposure tools were running in-line with various photoresist coat and develop tracks. The lithography tools were used to build both 64M and 256M DRAM devices and aggressive test vehicles. The process capability of the initial 0.25 micrometers reference process was done and compared to the 200mm data set of the sister factory. Automation issues for lithography tools were addressed and the cost metrics were calculated. SC300 demonstrated that a manufacturable 300mm lithography tool set and process for various ground rule devices was possible with the required performance in image transfer, CD control, and overlay. Further testing on 0.18micrometers and 0.15micrometers ground rule features indicated a sufficient process window for potential manufacturing. Additionally, it was demonstrated that non-concentric subfield stepping was feasible.
SEMICONDUCTOR300 was the first pilot production facility for 300mm wafers in the world. This company, a joint venture between Infineon Technologies Motorola, started in early 1998 to develop processes and manufacture products using 300mm wafer tool set. The lithography tools include I-line steppers, as I-line scanner, a DUV stepper, and DUV scanners. All of these exposure tools are running in-line with a photoresist coat and develop track. The lithography tools are used to build 64Mb DRAM devices and aggressive test vehicles with design rules of 0.25 micrometers and below, in sufficient quantity to be able to assess the tool readiness. This paper present the history of technical improvements and roadblocks that have occurred on the 300mm lithography tool set since the start-up, and describe a methodology used to assess the tool performance.
SEMICONDUCTOR300 was the first pilot production facility for 300mm wafers in the world. This company, a joint venture between Infineon Technologies and Motorola, is working to develop a manufacturable 300mm wafer tool set. The lithography tools include I-line steppers, a DUV stepper, and two DUV scanners. These tools are used to build 64M DRAM devices and aggressive test vehicles. Data will be presented on the mix-and-matching performance between DUV scanners and I-line steppers. Process-related data on CD within-field and across wafer sampling for selected tool types were investigated. The process capability of the current tool set for 0.25 micrometers and 0.18 micrometers devices were compared. Resolution performance of the scanner with its 0.68 numerical aperture was studied. Dense and isolated printed pattern performance was measured with in-line metrology. 300mm wafers are sensitive to backside defectivity, and therefore the wafer chuck design plays an important role in achieving the desired pattern transfer performance. The performance of the different chuck types and their sensitivity to incoming backside wafer contamination levels was studied. Rework data was used to assist in characterizing the exposure dose matching and chuck type performance.
SEMICONDUCTOR3000 was the first pilot production facility for 300nm wafers in the world. This company, a joint venture between Infineon Technologies and Motorola, is working to develop a manufacturable 300mm wafer tool set. The lithography tools include I-line stepper, and two DUV scanners. These tools are used to build both 64M DRAM devices and aggressive test vehicles. This paper shows the influence of non-linear errors on 300nm wafers is much stronger than on 200mm wafers. The team determined the root causes for the stronger appearance of these effects and proposed solutions to improve the overlay performance.
While integrated circuit manufacturing has demonstrated continuous productivity improvement over the last twenty years (as driven by Moore's Law), there remain significant areas for improvement. The lithographic tools in current factories have set the example in productivity improvement. They have evolved from individual tools for vapor prime, coat, expose, bake operations to integrated exposure tools and photoresist tracks that handle wafers sequentially from a load port until they return to the same load port. This paper examines the next logical step in this evolution resulting in the formation of a lithography (Litho) cluster by adding metrology for critical dimension (CD) and overlay measurements and optical inspection. Since with sampling of selected sites and wafers, CD and overlay measurements are relatively quick processes, one or more lithography photocells (exposure tool and photoresist track combinations) could be integrated to one set of centrally located metrology tools. Alternatively, simpler and smaller metrology modules could be integrated into each Litho cluster tool. Since the load ports and robotics could be shared and the total number of metrology tools in the factory is expected to increase dramatically, cost reduction and economies of scale in this combination of tools may be achieved. The benefits are estimated to be a 20% improvement in cycle time and simplified material handling.
SEMICONDUCTOR300 (SC300) is the first pilot manufacturing facility for 300 mm wafers in the world. This company, a joint venture between Infineon Technologies and Motorola, is working on developing a 300 mm manufacturing tool set. The pilot line contains a full compliment of tools for 0.24 micrometer ground rule 64 M DRAM manufacturing. The 64 M DRAM was chosen for the ability to easily benchmark against 200 mm 64 M DRAM manufacturing data from the sister factory. Currently, testing on structures with less than 0.20 micrometer ground rules is occurring the pilot line. In this paper we present the performance of the initial lithography tool set installed at SC300. Several lots of wafers with measurable yield have been produced. These lots have produced data on overlay, critical dimensions, and run-to-run, wafer-to-wafer and within-wafer performance of the various lithography layers. We now have preliminary data on the comparison of 200 mm tools to 300 mm tools in terms of footprint, throughput, reliability, and productivity gains for equivalent square centimeters of silicon. With this data we can start to predict what performance we should expect from 300 mm manufacturing lithography tools.
Semiconductor 300 is the first pilot manufacturing facility for 300mm wafers in the world. This company is a joint venture between Siemens and Motorola, formed for the purpose of developing a 300mm manufacturing tool set. The pilot line contains a full compliment of tools for DRAM manufacturing. This paper discusses the performance of the initial 300mm lithography tool set installed in our pilot line in Dresden, Germany. The product used for evaluating and debugging the tool set is a 0.25-micron ground rule 64 Meg DRAM. This was chosen for the ability to easily benchmark against 200mm DRAM manufacturing data. We have produced several lots of wafers with measurable yield. These lots have produced data on overlay, CD and run to run performance of the lithography tools on actual product. We have data on resist coating, and develop uniformity. With several lithography tools installed we have generated a large amount of mix and match data. In addition several challenges for successful lithography have surfaced related entirely to the increase in wafer size. Film, etch, polish and thermal non-uniformity have impacted the throughput and performance of the lithography tools. The installation of the first integrated 300mm pilot line has also produced data on the impact larger wafer size has on tool logistics, for example fab layout, installation schedules and wafer and lot transport. While technical data is always important, the main reason for converting to 300mm is economic. We now have preliminary data on the comparison of 200 tools to 300mm tools in terms of footprint, throughput, and productivity gains for equivalent square centimeters of silicon. With this data we can start to make preliminary recommendations for 300mm manufacturing tools.
This paper uses simulation and experiment to study near resolution limit patterning of contacts and damascene trenches using conventional i-line lithography. Special attention is paid to the requirements for substrate control. The patterning behavior is compared to DUV lithography results. We also evaluate the cost-of-process for an i-line process using substrate and optical enhancements compared to a standard 248 nm DUV process.
DUV scanning exposure systems have been steadily gaining market acceptance for the past five years, and soon, all major suppliers will offer 248-nm scanning tools. One of the major reasons for the emergence of this technology has been the purported improvement in critical dimension (CD) uniformity across the scanned field versus what can be realized in a full field stepper. Using high precision electrical resistance CD metrology, we have characterized the across field CD control capability of several DUV scanning tools and DUV steppers. Analysis is carried out through focus for multiple linetypes representing various orientations and nearest-neighbor proximities. Where possible, different NA/(sigma) combinations are examined as well. Surprisingly good full field sub-0.20 micrometers CD control is obtained even for 0.50 NA, and higher NA allows for non zero process latitude at 0.14 micrometers geometries. While it was initially anticipated that 193 nm ArF lithography would be required for 0.18 micrometers technology manufacturing, it has become apparent that 248 nm lithography will be employed for these groundrules, particularly for logic applications with predominantly semi-isolated features.
KEYWORDS: Lithography, Optical lithography, Deep ultraviolet, Systems modeling, Manufacturing, Data modeling, Optics manufacturing, Software development, Performance modeling, Control systems
This paper describes a high-leverage cost-reduction methodology -- advanced mix-and-match lithography. Quantifying the areas of cost savings and cost of ownership is essential in determining the optimum mix-and-match approach. Cost of ownership, using operating data coupled with quantitative models, is analyzed for a half-micron 200 mm fabrication line producing 16 Mbit DRAMs. Utilizing advanced lithography clusters to process the critical levels and cost-effective high-productivity cluster systems for the non-critical levels has resulted in a net production cost savings in excess of 30%. Data comparisons are made between process enhancements and tool types. Areas of cost savings are identified individually and ranked. Further, tradeoffs in learning, cycle time, and technology extendibility are also considered. The cost/benefit analysis demonstrates that mix-and-match lithography is a highly effective method for reducing lithography costs. This paper also discusses the increasing importance of cost modeling to improve competitiveness.
This paper describes the computer simulation results of 0.5 micrometers lithography for a 16 Mb DRAM. The model demonstrates, via aerial profiles, the increased focus latitude for deep- ultraviolet (DUV) lithography as compared to i-line lithography. The result translates into a larger process window for manufacturing DRAMs using DUV lithography. The model also isolated an imaging problem at one of the critical levels. Two probable solutions were simulated and then lithographically confirmed.
We have found that the performance of the t-BOC/onium salt resist system is severely degraded by vapor from organic bases. This effect is very pronounced and can be observed when the coated wafers stand for 15 minutes in air containing as little as 15 parts per billion (ppb) of an organic base. The observed effect, caused by this chemical contamination, depends on the tone of the resist system. For negative tone systems the UV exposure dose, required to obtain the correct linewidth, increases. While for the positive tone system, one observes the generation of a skin at the resist-air interface. Both effects are caused by the photogenerated acid being neutralized by the airborne organic base. There are a wide variety of commonly used materials which can liberate trace amounts of volatile amines and degrade resist performance. For example, fresh paint on a laboratory wall can exhibit this detrimental effect. These effects can be minimized by storing and processing the resist coated wafers in air that has passed through a specially designed, high efficiency carbon filter. The implementation of localized air filtration, to bathe the resist in chemically pure air, enabled this resist system to operate in a manufacturing environment at a rate of 100 wafers/hour.
This paper describes methods used and results obtained in the production of 1-megabit
(Mb) DRAM chips, using a chemically amplified tertiary-butoxy carhonyl
hydroxystyrene (t-BOC) resist and 1X lithography. 'Flie internally developed resist
provided high sensitivity and contrast, for I rn resolution on a Perkin Elmer Micralign
model 500 (PE 500) in the deep UV. Characterization, and modification of the PE 500
were required for this first application in the deep UV. The manufacturing process had
photo limited yield in excess of 95% with throughput of 100 wafers per hour.
Each DRAM design generation has required higher reoiution imaging and overlay capability. The 500-nm lithographic ground rules of a 16-Mb chip make deep-UV (DUV) an attractive alternative to,thc more stanth,rd mid-UV (MUV) photolithography presently practiced for less demanding technologies. The shorter wavelength permits an unproved depth of focus by allowing the same resolution at smaller numerical apertures. This approach retains the simplicity of single-layer-resist processing rather th a ii forcing conversion to m ultilayer imaging.
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