The evolution of the photolithographic model has enabled the semiconductor industry to achieve enhanced device efficiency within the consumer electronics domain through the ability to create diminutive shapes and sizes. This historical progression can be delineated into six discernible periods, all of which are based on fundamental elements of a light source and a lens: broadband, i-line, KrF (248nm), dry ArF (193nm), immersion (193nm), and the present environment belonging to the dynamic and evolving Extreme Ultraviolet (EUV) generation (13.5nm). Accompanied by this evolution, three supplementary patterning modalities have synergistically evolved to augment and extend the capacities of the lithographic approaches: Reactive Ion Etching (RIE), Chemical Mechanical Planarization (CMP) and Atomic Layer Deposition (ALD). The current EUV generation presents unique scaling challenges such as overlay discrepancies, critical dimension (CD) variance, and EUV exposure capacity limitations. To mitigate these scaling impediments and continue the miniaturization trajectory, Directed Self-Assembly (DSA) represents the nascent fourth era of complimentary patterning. DSA has the potential to tackle the foremost triad of scaling challenges pervading the contemporary industry landscape. In this discourse, we shall explain the profound role of DSA in the future of semiconductor fabrication. Specifically, we will critically assess the readiness to produce DSA materials and their potential for continued extension beyond the existing PS-b-PMMA generation platform.
The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer.
This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.
EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve
throughput has primarily been through a significant focus on source power which has been a continuing challenge
for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double
patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm
self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with
shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the
resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for
the patterned CD.
With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed
resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements
for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry
where the relaxation of both LER and CD together combined, give the resist formulation space a new target when
EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final
16nm half pitch target pattern to align with the industry needs.
If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow
proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed
process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added
costs associated with the double patterning process. This flow can then be shown to be an enabling approach for
many EUV applications.
EUV technology has steadily progressed over the years including the introduction of a pre-production NXE:3100 scanner that has enabled EUV process development to advance one step closer to production. We have carried out the integration with 20/14nm metal layer design rules converting double patterning with ArF immersion process to EUV with a single patterning solution utilizing a NXE3100 exposure tool. The exercise through the integration of a mature test chip with an EUV level has allowed us to have early assessment of the process challenges and new workflow required to enable EUV to the mass production stage. Utilizing the NXE3100 in IMEC, we have developed an OPC model and a lithography process to support 20/14nm node EUV wafer integration of a metal layer in conjunction with immersion ArF. This allows early assessment of mix-and-match overlay for EUV to immersion system that is critical for EUV insertion strategy as well as further understanding of the litho process, OPC, and mask defect control specific to EUV single patterning. Through this work we have demonstrated high wafer yields on a 20nm test vehicle utilizing single EUV Metal layer along with additional ArF immersion levels. We were able to successfully demonstrate low mask defectivity and good via chain and open/short electrical yield. This paper summarize the learning cycles from mask defect mitigation and mix machine overlay through post metal CMP wafer integration highlighting the key accomplishments and future challenges.
The objective of this work is to describe the advances in 193nm photoresists using negative tone
developer and key challenges associated with 20nm and beyond technology nodes.
Unlike positive tone resists which use protected polymer as the etch block, negative tone
developer resists must adhere to a substrate with a deprotected polymer matrix; this poses
adhesion and bonding challenges for this new patterning technology. This problem can be
addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in
them (SiARC), which are specifically tailored for compatibility with the solvent developing
resist. We characterized these modified SiARC materials and found improvement in pattern
collapse thru-pitches down to 100nm.
Fundamental studies were carried out to understand the interactions between the resist materials
and the developers. Different types of developers were evaluated and the best candidate was
down selected for contact holes and line space applications. The negative tone developer
proximity behavior has been investigated through optical proximity correction (OPC)
verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to
less than 100 adders/wafer by optimizing the develop process. Electric yield test has been
conducted and compared between positive tone and negative tone developer strategies. In
addition, we have done extensive experimental work to reduce negative tone developer volume
per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of
positive tone CoO.
The physical processes that underpin a recently developed commercial stochastic resist model are introduced and the model details discussed. The model is calibrated to experimental data for a commercially available immersion chemically amplified photoresist using basic physical information about the resist and an iterative fitting procedure. This data comprises CD (critical dimension) and LWR (linewidth roughness) measurements through focus and exposure for three separate line-type features on varying pitches: dense, semidense, and isolated. A root mean square error (RMSE) of 2.0 nm is observed between the calibrated model and the experimental CD data. The ability of the calibrated model to predict experimentally observed CD uniformity distributions is tested for a variety of 1-D and 2-D patterns under fixed focus and exposure conditions. The subnanometer RMSE obtained between experiment and simulation suggests that the calibrated stochastic model has excellent predictive power for a variety of applications.
KEYWORDS: Stochastic processes, Calibration, Data modeling, Lithography, Line width roughness, Semiconducting wafers, Monte Carlo methods, Scanning electron microscopy, Finite element methods, Photoresist materials
A newly developed stochastic resist model, implemented in a prototype version of the PROLITH
lithography simulation software is fitted to experimental data for a commercially available immersion ArF
photoresist, EPIC 2013 (Dow Electronic Materials). Calibration is performed only considering the mean CD
value through focus and dose for three line/space features of varying pitch (dense, semi-dense and isolated).
An unweighted Root Mean Squared Error (RMSE) of approximately 2.0 nm is observed when the calibrated
model is compared to the experimental data. Although the model is calibrated only to mean CD values, it is
able to accurately predict LER through focus to better than 1.5 nm RMSE and highly accurate CDU
distributions at fixed focus and dose conditions. It is also shown how a stochastic model can be used to the
describe the bridging behavior often observed at marginal focus and exposure conditions.
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