A critical challenge in semiconductor manufacturing is the high electricity consumption, especially by lithography tools, which significantly contribute to the industry's environmental impact. For lithography track systems, reducing the energy consumption of hotplate processes is essential due to their high energy demands. This study introduces an innovative, energy-efficient process that offers a viable alternative to conventional thermal crosslinking systems for Spin-On Carbon (SOC) and spin-on glass (SOG) underlayers, which typically require high temperatures for full film densification. The proposed method utilizes an overall-wafer optical exposure system, integrated on SCREEN’s DT-3000 track, to crosslink underlayer materials designed by Brewer Science to cure through light exposure. This paper demonstrates how this optical crosslinking approach can achieve substantial energy savings of 85% for SOC and 60% for SOG, while maintaining lithographic performance. The transition from a traditional hotplate process to a light-curing mechanism is thoroughly examined from multiple perspectives.
As the resource-intensive semiconductor industry progresses, concerns about environmental sustainability are intensifying, and efforts to achieve sustainable chip manufacturing are accelerating. As the complexity of process steps and nodes increases significantly to achieve narrower pitches, the lithography process, which consumes a substantial amount of power, has emerged as a critical issue in terms of electrical energy consumption. We propose a novel process that substantially reduces electricity consumption as a feasible alternative to the conventional thermal crosslinking approach. We provide a comprehensive discussion of an optical crosslinking system designed to crosslink underlayer materials, such as spin-on carbon and spin-on glass, solely through light exposure, thereby eliminating the need for heat. By replacing the traditional thermal baking system, which is energy-intensive, with the energy-efficient optical crosslinking system, we demonstrate the potential to save both energy and processing time on the track without compromising lithographic performance. To validate the feasibility of the proposed approach and materials, we conducted film crosslinking confirmation and etch rate tests using light-curable underlayer materials. Subsequently, we analyzed and evaluated the performance of pitch 28 nm line/space patterning under optimized curing conditions. The patterning tests with light-curable underlayers yielded competitive results compared with those with the thermal underlayer. The introduction of the innovative optical crosslinking system can contribute to harmonizing environmental sustainability with the semiconductor industry, providing ecological benefits and facilitating sustainable semiconductor manufacturing.
As the awareness of climate change and sustainability grows, industries are placing more commitment to reduce their environmental footprint. Semiconductor companies are no exception, and many are now working to reduce their greenhouse gas (GHG) emissions and adopt greener practices as crucial steps towards a more environmentally responsible future. Amongst the top sustainability challenges faced in semiconductor manufacturing, electricity consumption emerges as a critical concern, with lithography tools requiring a substantial amount of energy to operate. As a track vendor, reducing energy consumption and optimizing tool efficiency are ongoing challenges at SCREEN, where hotplate processes rank amongst the most energy-intensive operations, especially during the bake of underlayer materials that require high temperatures to achieve full film densification. This paper shows an innovative energy-efficient process as a viable alternative to conventional spin-on carbon (SOC) and spin-on glass (SOG) thermal crosslinking systems. We deeply explore the feasibility to use an overall-wafer exposure system integrated on SCREEN’s DT-3000 track to harden underlayer materials specifically designed to crosslink via light, without the need of heat. We demonstrate how migration from a hotplate process to a 100% optical curing mechanism can lead to outstanding savings in energy and process time, while keeping the lithographic performance.
In the ever-evolving landscape of semiconductor manufacturing, ensuring impeccable process stability and defect control remains crucial in modern lithography. These elements have driven the maturation of the entire extreme ultraviolet (EUV) lithography ecosystem, which is now geared to meet the upcoming challenges. A critical component of this ecosystem is the lithography track, whose performance capabilities have been evolving rapidly to keep pace with technology roadmap advancements. In this study, we present the capabilities of novel hardware solutions integrated into SCREEN's DT-3000 coat-develop track system when applied to metal oxide resist (MOR) platforms. We demonstrate how hardware development remains a fundamental driver for enhancing not only process stability and defect control but also for optimizing additional critical metrics such as resolution, line width roughness (LWR), defect-free window, and pattern shape. These advancements underscore the continued importance of hardware innovation in the semiconductor manufacturing landscape and its indispensable role in supporting the transition to high-NA EUVL technology, ensuring high-quality and reliable production.
KEYWORDS: Power consumption, Etching, Spin on carbon materials, Semiconductors, Optical lithography, Line edge roughness, Thermography, Extreme ultraviolet lithography, Lithography, Industry
Underlayer materials account for the majority of electricity consumption in the lithography process because all tracks need to maintain a high temperature not only during the process time but also throughout the entire operational period. In this study, we propose a novel method that deviates from the conventional approach of utilizing thermoplastic materials as the underlayers for crosslinking, instead advocating for the use of light source for the crosslinking process, which potentially leads to reduced electricity consumption. Furthermore, some studies have shown that light-curable materials exhibit a higher degree of crosslinking compared to thermally cured materials, which implies that better crosslinking may provide better lithography performance. We evaluated light-curable materials based on the thermoplastic underlayers used in conventional EUV lithography.
The next generation of this technology (using a high-numerical aperture (NA) at 0.55 compared to the present at 0.33) is also currently being prepared and is scheduled to be production ready within the next few years. However, it is well known that the application of higher NA will lead to smaller depth of focus (DOF). The DOF with NA 0.55 systems will reduce to 1/3 of the value that we have in current 0.33 NA systems, i.e. if DOF at NA 0.33 is 100nm then at NA 0.55, DOF will be around 30 to 40nm. At these exposure conditions, wafer surface distortions as an effect of backside defects will become significant concern. In this study, the wafer backside at exactly the same locations detected as where these abnormal CD’s were detected on wafer frontside. And the evidence was shown that the backside defects affected to frontside pattern deformation. Furthermore, it was found that an effective backside cleaning process can mitigate pattern defocus caused by these wafer backside particles.
The microchip fabrication process consists of hundreds of steps, where each step can contribute to the backside contamination of the wafer. When clamping a wafer in the exposure tool, the presence of backside defects can lead to various issues, including local deformation of the wafer or clamping distortions, that result in focus loss or on-product overlay drifts in that area. With device scaling and the introduction of High NA EUV, we anticipate backside defects to be a more severe problem for frontside patterns. The lenses of 0.55 NA EUV systems will have a very small depth of focus compared to 0.33 NA EUV scanners, meaning that a defect present on the wafer backside can easily translate into frontside pattern failures. Additionally, backside contamination increases the risk of damage to the scanner wafer-table (WT) having a negative impact on its lifetime, maintenance cost and productivity. In this work, to better understand the impact of backside contamination on the EUV patterning performance, a new characterization approach was set up based on an optical inspection technique, Pattern Shift Response PSR. Together with SCREEN, we could demonstrate a good correlation between backside contamination, detected by the levelling measurements from the NXE3400B, and frontside pattern distortions. Additionally, the impact of backside contamination on wafer CD uniformity was investigated by measuring CD across. We confirmed that by using more robust cleaning techniques we were able to reduce the number of backside defects and increase wafer yield.
In this paper, we share some early results on using EUV to pattern the Storage Node Landing Pad + Bit Line Peri. We use advanced processing techniques on the track, as well as advanced machine learning-based metrology to characterize the process. We have used a MOR to pattern the SNLP+BLP layer. In Figure 1 we show a SNLP+BLP design clip and the different sources which were optimized for the different pitches as well as a schematic of the process. Optimization with freeform sources was done to improve the pattern fidelity of these complex 2D patterns. In an attempt to improve CDU performance and reduce process variability, several approaches were investigated using SCREEN’s DT-3000 track. Amongst these approaches, a novel hotplate technology incorporating multi-zone temperature control was extensively explored during the PEB process, to deliver ultimate CD stability. SEM images acquired were denoised with advanced algorithms to better understand minute variations in pattern fidelity.
As technology advances, the need for precise and reliable track systems became crucial to enable high-performance and reliable semiconductor manufacturing. Progressive track development boosts several metrics like defectivity, critical dimension uniformity (CDU), line width roughness (LWR) and pattern shape. In this work, we investigate and improve the defect levels for different EUV resist platforms using SCREEN’s DT-3000 coat-develop track system. Additionally, we showcase the recent advancements on DT-3000 track to improve CD uniformity, a metric that plays a vital role in EUVL as it ensures consistent and precise dimensions printed on the chips. Through an innovative post-exposure bake hotplate design, we introduce a pioneer solution to correct process fingerprints that affect the CD stability across the wafer, thus meeting the challenging demands of advanced generation semiconductor manufacturing.
While several leading semiconductor manufacturers are already heavily investing in the development of high-NA EUV technology, there are still some technical challenges to overcome. Photoresists are identified as main drivers to achieve the required ultimate resolution, with the development of new EUV materials being ranked as one of the top priorities to address. Currently, MOR is the primary candidate for patterning at 0.55NA relevant pitches, but stability still must be demonstrated. The aim of this work was to extend the current knowledge about the impact of delay effects on resist stability. The effect of post-coating, post-exposure and post-PEB delay on litho performance were thoroughly analyzed and compared for metal oxide and main-chain scission resist platforms. It has been observed that for both chemistries, track stand-alone processing might be a possible and effective approach to explore towards high-NA, bringing more flexibility and enabling higher throughput.
KEYWORDS: Process control, Critical dimension metrology, Back end of line, Optical lithography, Extreme ultraviolet lithography, Metals, Thermal stability, Temperature control, Semiconductors, Semiconducting wafers
This paper explores the effects of optimizing the post-exposure bake (PEB) process on controlling the variability of Tip-To-Tip (T2T) structures within metallization layers. To gauge variability control, we evaluated Local Critical Dimension Uniformity (LCDU) and Global Critical Dimension Uniformity (GCDU) during the After Development Inspection (ADI) phase. Each of the PEB process optimizations had a unique impact on both LCDU and GCDU. The combination of adjusting the PEB temperature and optimizing the PEB chamber environment produced the most favorable results. This led to a notable improvement of 18.4% in LCDU and 20.1% in GCDU, respectively.
Control of wafer backside defectivity is a challenge during the chip manufacturing process and has been extensively investigated throughout the past decade, especially on immersion lithography systems. As technology nodes continue to scale down and we approach the high NA EUV lithography era, backside contamination is becoming a critical problem. High NA EUV exposure systems have a smaller depth of focus compared to low NA EUV systems. The presence of backside wafer defects can easily lead to focus loss or on-product overlay errors leading to pattern failures. To anticipate the upcoming challenges, SCREEN has developed a sophisticated track-integrated backside cleaning (BSC) module on the DT-3000 system. This enables an advanced post-coating BSC solution directly before exposure. Together ASML, imec and SCREEN, investigated the potential of this unique BSC process to extend the lithographic performance of EUV material stacks, by correlating backside contamination with frontside patterning performance and the minimization of scanner focus spots. With this approach, we try to identify and characterize potential backside defect killers that could cause not only yield loss, but also physical deterioration of the scanner wafer table (WT) and its lifetime.
Owing to photon shot noise and inhomogeneous distribution of the molecular components in a chemically amplified resist, resist patterns defined by extreme ultraviolet (EUV) lithography tend to suffer from stochastic variations. These stochastic variations are becoming more severe as critical dimensions continue to scale down, and can thus be expected to be a major challenge for the future use of single exposure EUV lithography. Complementing EUV lithography with directed self-assembly (DSA) of block-copolymers provides an interesting opportunity to mitigate the variability related to EUV stochastics. In this work, the DSA rectification process at imec is described for both line/space (L/S) and hexagonal contact hole (HEXCH) patterns. The benefits that rectification can bring, as well as the challenges for further improvement are being addressed based on the current status of imec’s rectification process.
For printing the most critical features in semiconductor devices, single exposure extreme ultraviolet (EUV) lithography is quickly advancing as a replacement for ArF immersion-based multipatterning approaches. However, the transition from 193 nm to 13.5 nm light is severely limiting the number of photons produced by a given source power, leading to photon shot noise in EUV patterns. In addition, inhomogeneous distribution of components inside conventional photoresists is adding to the printing variability, especially when critical dimensions continue to shrink. As a result, stochastic issues leading to rough, non-uniform, and potentially defective patterns have become a major challenge for EUV lithography. A promising solution for this top-down patterning approach is complementing it with bottom-up directed self-assembly (DSA) of block copolymers. In combination with 193i lithography, DSA of lamellae forming block copolymers has previously shown favorable results for defining dense line-space patterns using LiNe flow.1 In this study, we investigate the complementarity of EUV + DSA for rectification of pitch 28 nm line-space patterns. Roughness and defectivity are critical factors that need to be controlled to make these patterns industrially relevant. We look at the impact of DSA material and processing parameters on line edge roughness and line width roughness in order to identify and mitigate the origins of pattern roughness. On the other hand, we also assess the different types of defect modes that are observed by means of optical defect inspection and ebeam review, and study the root causes for their formation. To wrap-up, the benefits of 1X DSA versus 3X DSA are presented by comparing EUV + DSA to LiNe flow.
As technology nodes continue to scale down, the full ecosystem around Extreme Ultraviolet Lithography (EUVL) is becoming more mature and proactive in the anticipation of upcoming challenges. To keep up with the technology roadmap evolution, lithography track performance capabilities have also been rapidly expanding through the years and new modules are being specially designed to support the lithographic performance improvement of different materials. In this work, we showcase the capability of novel hardware solutions currently available on SCREEN’s DT-3000 coat-develop track system. Based on a holistic approach, we demonstrate how hardware development is still a key not only to improve process stability and drive down defectivity to historically low levels but also to boost other metrics such as line width roughness (LWR), defect-free process window, and pattern shape.
Currently, there are many developments in the field of EUV lithography that are helping to move it towards increased high volume manufacturing (HVM) feasibility. Targeted improvements in hardware design for advanced lithography are of key interest to our group, specifically metrics such as line width roughness (LWR) smoothing, dose reduction processes, and defect mitigation. In this study, we investigate how novel hardware solutions currently available on our SCREEN DT-3000 coat-develop track system, can be used as complementary non-patterning approaches to boost resist scaling even further. The utility of SCREEN non-standard hardware features to enhance overall lithography performance of a main chain scission EUV resist was deeply explored, and new process approaches were successfully identified. We hereby present our work utilizing the SCREEN DT- 3000 coat-develop track system with an ASML NXE:3400 to improve sensitivity, CD uniformity, line width roughness, and defectivity levels of aggressive dense L/S patterns.
The availability of EUV lithography is the mainstream for resolving critical dimension of the advanced technology nodes, currently in the range of 18nm and below [1]. The first insertion of EUVL into manufacturing utilizes chemically amplified resist (CAR) [2]. The filtration of CAR, both at bulk and point-of-use (POU), has already demonstrated in ArF and ArF immersion lithography to play a significant role for microbridges reduction essentially by removing hard particle and gels [3-6]. With respect to ArFi, EUV is bringing new challenges not only for the achievement of the required line roughness, sensitivity and resolution, but also for the need of a substantial reduction of defects such as line collapse, microbridges and broken lines. In this study, it demonstrated the ability of utilizing novel POU filtration to modulate microbridges and achieving superior start-up behavior, both crucial for enabling EUVL at high volume manufacturing. Different POU filters were tested at the imec EUV cluster comprised of TEL CleanTrack LITHIUS Pro-Z and ASML NXE:3400B. The start-up performance, assessed by measuring defects down to 19nm size as a function of the flushing solvent volume, has shown the fast achievement of attaining a stable baseline. Lithography experiments targeting reduction of on-wafer defectivity, carried out with commercially available photoresists, have consistently shown a substantial reduction of after resist development (ADI) and after resist etch (AEI) microbridges on a 16nm L/S test vehicles. The effect of membrane physical intrinsic designs and novel cleaning of POU devices are discussed.
Currently, there are many developments in the field of advanced lithography that are helping to move it towards increased HVM feasibility1,2,3,4. Targeted improvements in hardware design for advanced lithography are of interest to our group specifically for HVM metrics such as LWR improvement, dose reduction processes, and defect density reduction. In this work we are building on our experience to improve LWR in an advanced lithographic process by employing novel hardware solutions on our SCREEN DUO coat develop track system5 . Our approach is to implement post-litho annealing to improve resist line roughness. Although it is preferable to achieve such improvements post-etch process we feel, as many do, that post-patterning improvements are a precursor to improvements after etching6 . We hereby present our work utilizing the SCREEN DUO coat develop track system to improve aggressive dense L/S patterns.
KEYWORDS: Lithography, Photoresist materials, Immersion lithography, Semiconducting wafers, Line width roughness, Line edge roughness, Scanning electron microscopy, Particles, Bridges, Finite element methods, Fermium, Frequency modulation
Specific “killer-defects”, such as micro-line-bridges are one of the key challenges in photolithography’s advanced applications, such as multi-pattern. These defects generate from several sources and are very difficult to eliminate. Pointof-use filtration (POU) plays a crucial role on the mitigation, or elimination, of such defects. Previous studies have demonstrated how the contribution of POU filtration could not be studied independently from photoresists design and track hardware settings. Specifically, we investigated how an effective combination of optimized photoresist, filtration rate, filtration pressure, membrane and device cleaning, and single and multilayer filter membranes at optimized pore size could modulate the occurrence of such defects [1, 2, 3 and 4]. However, the ultimate desired behavior for POU filtration is the selective retention of defect precursor molecules contained in commercially available photoresist. This optimal behavior can be achieved via customized membrane functionalization. Membrane functionalization provides additional non-sieving interactions which combined with efficient size exclusion can selectively capture certain defect precursors. The goal of this study is to provide a comprehensive assessment of membrane functionalization applied on an asymmetric ultra-high molecular weight polyethylene (UPE) membrane at different pore size. Defectivity transferred in a 45 nm line 55 nm space (45L/55S) pattern, created through 193 nm immersion (193i) lithography with a positive tone chemically amplified resist (PT-CAR), has been evaluated on organic under-layer coated wafers. Lithography performance, such as critical dimensions (CD), line width roughness (LWR) and focus energy matrix (FEM) is also assessed.
Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies.
Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development.
Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.