Due to assembly processes in microelectronics packaging, semiconductor materials are under undesired stresses, which become more important at extreme thermo-mechanical operating conditions. Investigations of the performances of the semiconductors is very challenging, because each assembly is a complex structure with many materials with very different physical-chemical properties. Remarkable is the determination of local stresses trough optical techniques, like Raman spectroscopy. Focus of this study is the monitoring of stress induced on silicon chips after bonding. Three bonding processes are investigated: soldering using a eutectic AuSn preform, sintering using a commercial Ag sintering paste, sintering using an in-house developed sintering paste made by surface enhanced etched brass particles dispersed in polyethylene glycol 600. In all cases, the Si-chip is bonded to a Cu substrate. The stress distribution after AuSn-soldering presents a homogeneous pattern, while after Ag- and Cu-sintering an axial distribution along the diagonal is observed. The samples are investigated at three temperatures: -50, 20, and 180 °C. The stress phenomena are higher for the assemblies made via AuSn-soldering, with stress value above 600 MPa. The results are discussed in term of compressive and tensile strain and thermal expansion coefficients.
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