Dr. Jac Paul Condella Profile

Dr. Jac Paul Condella

OPC Engineer at Cadence Design Systems Inc

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Author

Publications (7)

Proceedings Article | 11 April 2024 Presentation + Paper

In-design DFM pattern optimization with ML models for dynamic fixing guidance selection and implementation

Fadi Batarseh, Piyush Pathak, Jac Condella, Keerthana Bhoopanam, Jeff Nelson, Lynn Wang, Ya-Chieh Lai

Proceedings Volume 12954, 1295406 (2024) https://doi.org/10.1117/12.3023887

KEYWORDS: Design for manufacturing, Design, Machine learning, Mathematical optimization, Manufacturing, Design for manufacturability, Education and training, Process modeling, Histograms, Electronic design automation

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Proceedings Article | 10 April 2024 Presentation + Paper

Transistor profiling for quantitative evaluation of variability in transistor characteristics due to layout dependent effects (LDEs)

Chikaaki Kodama, Mikiyasu Yamaji, Hiroshi Kitahara, Akira Hokazono, Shigeki Nojima, Piyush Pathak, Kimiko Ichikawa, Jac Paul Condella, Michel Cote, Ya-Chieh Lai, Philippe Hurat

Proceedings Volume 12954, 1295403 (2024) https://doi.org/10.1117/12.3010201

KEYWORDS: Transistors, Profiling, Design, Device simulation, Image classification, Matrices, Very large scale integration, Computer simulations, CMOS technology

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Proceedings Article | 22 February 2021 Poster + Paper

Fast, high-capacity critical area analysis (CAA) with advanced FINFET defectivity calculation

Xiaoyuan Qi, Atul Chittora, Aaron Sinnott, Binod Kumar G. Nair, Shobhit Malik, Jeffrey Nelson, Jac Condella, Jonathan Fales, Rwik Sengupta, Ya-Chieh Lai, Frank Gennari, Philippe Hurat

Proceedings Volume 11614, 1161413 (2021) https://doi.org/10.1117/12.2583515

KEYWORDS: Fin field effect transistors, Transistors, Semiconductors, High volume manufacturing, Databases, Data modeling

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Proceedings Article | 23 March 2020 Presentation + Paper

Jaehwan Kim, Jin Kim, Byungchul Shin, Sangah Lee, Jae-Hyun Kang, Joong-Won Jeon, Piyush Pathak, Jac Condella, Frank Gennari, Philippe Hurat, Ya-Chieh Lai

Proceedings Volume 11328, 113280I (2020) https://doi.org/10.1117/12.2551970

KEYWORDS: Metals, Design for manufacturing, Chemical mechanical planarization, Silicon, Reliability, Optical proximity correction, Semiconducting wafers, Extreme ultraviolet lithography, Manufacturing, Yield improvement

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Proceedings Article | 5 April 2011 Paper

Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs

Philippe Hurat, Rasit Topaloglu, Ramez Nachman, Piyush Pathak, Jac Condella, Sriram Madhavan, Luigi Capodieci

Proceedings Volume 7974, 797412 (2011) https://doi.org/10.1117/12.882508

KEYWORDS: Transistors, Lithography, Standards development, Neodymium, Silicon, Data modeling, Statistical analysis, Device simulation, Calibration, Ions

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Proceedings Article | 19 March 2008 Paper

Context analysis and validation of lithography induced systematic variations in 65nm designs

Arjun Rajagopal, Anand Rajaram, Raguram Damodaran, Frank Cano, Srinivas Swaminathan, Clive Bittlestone, Mark Terry, Mark Mason, Yajun Ran, Haizhou Chen, Robert Ritchie, Bala Kasthuri, Jac Condella, Philippe Hurat, Nishath Verghese

Proceedings Volume 6925, 69250A (2008) https://doi.org/10.1117/12.778836

KEYWORDS: Silicon, Model-based design, Data modeling, Etching, Scanning electron microscopy, Transistors, Optical proximity correction, Lithography, Critical dimension metrology, Process modeling

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Proceedings Article | 4 March 2008 Paper

Microprocessor chip timing analysis using extraction of simulated silicon-calibrated contours

Toshiaki Yanagihara, Takeshi Hamamoto, Koya Sato, Atsushi Okamura, Toshiyuki Matsunaga, Naohiro Kobayashi, Tatsuya Maekawa, Nishath Verghese, Jac Condella, Philippe Hurat

Proceedings Volume 6925, 69250O (2008) https://doi.org/10.1117/12.773013

KEYWORDS: Silicon, Transistors, Clocks, Optical proximity correction, Etching, Data modeling, Shape analysis, Lithography, Databases, Picosecond phenomena

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Showing 5 of 7 publications

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