The Queensland Microtechnology Facility is an initiative of the Queensland Government in conjunction with Griffith University. The Queensland Government through its Smart State Research Facilities Funds (SSRFF) is providing funds for equipment to equip a purpose built building provided by the University. The focus of the Facility is on the application of Silicon Carbide on Silicon semiconductor systems. This is an important feature that enables access to the mature silicon technology at the same time providing access the less mature but very promising SiC technology and its properties. These properties include broad bandgap, thus high voltage and high temperature operations, excellent mobilities, very small leakage currents and high thermal conductivity. The QMF is unique in that it will encourage state of the art research with a commercial bias. It will be equipped with custom built equipment to meet the goals of the Facility. Already there are projects directed toward the exploitation of Silicon Carbide on Silicon Technology being undertaken. This paper provides some background to the planning process associated with the realisation of the QMF.
The possibility of using sputtered metals as mask materials for deep anisotropic chemical etching in silicon was investigated. Sputtered films of chrome, nickel and tungsten were all found to be chemically resistant to potassium hydroxide (KOH) and tetramethyl ammonium hydroxide (TMAOH). However as expected, these metals had poor adhesion to the silicon substrate. By comparison sputtered titanium was found to have excellent adhesion properties, and was chemically resistant to TMAOH but not to KOH. Resistance to KOH was achieved by thermal oxidation of the titanium film, at temperatures between 600 and 900° C. Following oxidation, etch depths more than 200μm were readily achieved in KOH etching. This makes sputtered titanium a potential alternative to the conventional mask material, silicon nitride, for the application of deep anisotropic etching. The reduction in etch rates due to a galvanic effect of conductive metal masks on silicon-on-insulator wafers was also investigated. It was observed that this effect was also overcome by thermal oxidation of the titanium mask.
In this paper we suggest a new near ideal memory technology to replace existing FLASH and DRAM, the new technology being based on the semiconducting material Silicon Carbide (SiC). The technology will not only be a replacement for FLASH and DRAM but will open up new and novel applications because of its unique capabilities. We provide the reasons why SiC will become the next generation memory material and suggest new structures that will be exploited by a new company QsRAM that will lead the market push for these new memories.
Development of a micromachined electrode array for cochlear implant application is presented. The device is constructed from a silicon substrate with sputtered platinum electrodes and connection tracks. Electrochemical impedance spectroscopy (EIS) is used to study the properties of the electrode, and to identify potential problems caused by the micromachining process and materials. A variety of insulators are studied and a two part epoxy is identified as an adequate insulator for operation under harsh electrochemical testing conditions. The semiconducting silicon substrate is found to contribute to the total impedance of the device at high frequencies due to the thin insulating oxide between the substrate and conducting tracks. This is a potential problem for micromachined electrodes operating under high frequencies or using square stimulating pulses. The charge-delivery properties are studied using electrochemical impedance spectroscopy. It is found that platinum sputtered under particular conditions results in excellent surface conditions for optimum charge-delivery.
This paper presents a new cost-effective fiber-to-waveguide coupling method for self-aligning optical fibers on silicon platforms, and for achieving optical quality end-polished silicon-on-insulator (SOI) single-mode rib waveguide devices using wet chemical micromachining techniques. Through accurate alignment to the <011> plane(s) of the (100) device layer of a SOI wafer, rib waveguide devices with self-alignment features are fabricated with the ends of each waveguide wet etched and concurrently polished providing an optical quality facet or fiber-to waveguide interface. Eliminating the need to saw cut and then mechanically polish the waveguide device ends, the overall fabrication process is simplified and provides a fiber alignment capability at the ends of the waveguide devices with an alignment accuracy limited by fiber size tolerance. Experimental measurements were carried out to verify the optical quality of the waveguide facets formed using this new technique, which proved excess facet losses of practically unmeasurable quantities. Both simulation and experimental results were obtained to verify the single-mode nature of the rib waveguides.
A new structure of SiC ACCUFET MOSFET for high power applications have been proposed and analyzed by simulation. The new MOSFET has an n-type ion implanted trench region and a MOS structure consisting of a thin surface layer of epitaxially grown n-type SiC. The current flows through then-type ion implanted region, then via accumulation channel of electrons defined in the epitaxially grown SiC surface layer. The thickness and doping of the n-type surface and p-type base epitaxially grown layers control the channel conditions. At zero gate bias the channel is fully depleted by the built-in fields of SiC p-base layer and the gate electrode resulting in a normally off device with the drain voltage supported by the n-drift region. Moreover, this designed structure fully addresses most of the open issues related to the MOS interface problems, i.e. low channel mobility and high electric field in the gate oxide of the MOS structure. 2D numerical simulations demonstrate that the optimized designed structure can withstand the blocking voltage of more than 1000 V, and a low specific on- resistance. The analytically calculated and simulated result son specific on-resistance of the optimized structure show as low a s 19.3 (Omega) cm2 specific on resistance can achieved with low gate bias of 5V.
The necessity to decrease silicon wafer-processing temperatures substantially has stimulated research into new and innovative techniques for the formation of thin dielectric films. A photo-decomposition technique using nitric oxide (NO) is one such promising method. Thermally NO-grown and NO-annealed dielectric film shave already shown very encouraging physical and electrical properties. The purpose of this study is to investigate the effect of UV irradiation on the growth kinetics and on the electrical and physical characteristics of these thin dielectrics and to simulate the decomposition of NO molecules that occurs thermally above 1000 degrees C. Methods using UV and vacuum UV light generated from low-pressure mercury or deuterium lamps to stimulate the growth of ultrathin dielectric films are described. Thin dielectrics were prepared by irradiating a UV beam on the heated silicon substrate covered by a thin layer of nitric oxide gas at different temperatures for various lengths of time. The films grown under the low- pressure mercury lamp displayed a much faster growth rate than under the deuterium lamp. The electrical characteristics of the films grown using a deuterium lamp show encouraging results compared to the low-pressure mercury. Compositions of the various dielectrics formed under the two UV sources were studied using x-ray photoelectron spectroscopy. MIS devices were fabricated using these films as gate insulators and were electrically characterized. Electrical and physical characterization revealed good film qualities, rendering this new UV-NO dielectric growth technique promising for low temperature semiconductor processing.
SiC MOSFETs are currently being developed for use in RF, microwave, and switch mode power supply applications, but the process conditions required for high quality and reliable oxides are not yet optimized. This paper present result of a fundamental study comparing wet and dry oxidation of SiC. Equivalent 4H-SiC substrates were cleaned and prepared under identical conditions before oxides were grown in either wet or dry ambients, followed by an inert gas anneal. Capacitance-voltage curves show increased net effective charge and density of interface states in the upper half of the SiC bandgap due to wet oxidation of n-SiC compared to dry oxidation. In contrast, wet oxidation of p- SiC reduces the density of donor-like states in the lower half of the SiC bandgap compared to dry oxidation. Current- voltage curves reveal more low-field leakage as a result of wet oxidation. When oxides on n-type substrates are stressed at room temperature using a dielectric field strength of 9MV/cm, increased hole trapping is seen at the oxide- semiconductor interface of wet oxide devices compared to dry oxide devices. Stressing at a higher temperature and lower field results in similar changes in net effective charge fort he two oxides, although the wet oxide shows considerably more increase in low-field leakage current.
This paper presents a new cost-effective fiber-to-waveguide coupling method for self-aligning optical fibers on silicon platforms, and for achieving optical quality end-polished silicon-on-insulator (SOI) single-mode rib waveguide devices using wet chemical micromachining techniques. Through accurate alignment to the plane(s) of the device layer of a SOI wafer, rib waveguide devices with self-alignment features are fabricated with the ends of each waveguide wet etched and concurrently polished providing an optical quality facet or fiber-to-waveguide interface. Eliminating the need to saw cut and then mechanically polish the waveguide device ends, the overall fabrication process is simplified and provides a fiber alignment capability at the ends of the waveguide devices with an alignment accuracy limited by fiber size tolerance. Experimental measurements were carried out to verify the optical quality of the waveguide facets formed using this new technique, which proved excess facet losses of practically unmeasurable quantities. Both simulation and experimental results were obtained to verify the single-mode nature of the rib waveguides.
A new design for the comb finger structures used in micromechanical electrostatic comb-drive actuators is presented. The new angled comb finger design is simulated using finite element analysis techniques and the results compared with hose obtained from the simulation of a conventional rectangular shaped comb finger. Results obtained demonstrate the greater actuation force generation capabilities of the new angled comb finger design. Actuation forces of up to 4.5 times those generated by standard comb finger designs have been obtained. Finally, a design approach has been demonstrated, allowing the successful design of a device based on the use of the new angled comb finger. This technique ensures the stability of the device throughout its operable range of displacements for both micron and sub-micron comb finger gap widths.
KEYWORDS: Semiconducting wafers, Manufacturing, Control systems, Oxides, Field effect transistors, Process control, Monte Carlo methods, Integrated circuits, Yield improvement, Etching
A study to investigate systematic ways of controlling parametric yield for future production of deep submicron MOSFETs has been performed. It is important to know how and where in the manufacturing process the parametric yield can be controlled most efficiently, because for these devices no manufacturing expertise has yet been accumulated. Our study is based on a comparative sensitivity analysis, which has revealed that yield control techniques employed in micron size devices may not be efficient in deep submicron size devices, making a reorientation for manufacturing control mandatory.
Indications are that very thin dielectrics needed for future generation of integrated circuits will be in a form of nitrogen-modified oxide. A significant amount of experimental data on growth kinetics for oxides grown/nitrided in N2O has been gathered. It appears that nitrogen neutralizes growth sites at the oxide-silicon interface, which significantly slows down the oxidation process when N2O is used as an oxidizing ambient. In this paper, the classic Deal-Grove formulation is extended to include the concentration of the growth sites. Also, the continuity equation applied to the growth sites is used to determine the concentration of the growth sites. This model has been incorporated into a TMA SUPREM-3 process simulator, and the model parameters calibrated with available experimental data. This provides not only the tool needed for process simulation, but also a better understanding of nitrogen modified oxide films.
Ultrathin (< 5 nm) dielectric films have been grown on (100) silicon using rapid thermal processing (RTP) in a nitric oxide (NO) ambient. The chemical composition was studied using x-ray photoelectron spectroscopy (XPS). Interface state density, charge trapping properties, and interface state generation during Fowler-Nordheim electron injection have also been investigated. The films grown in NO have excellent electrical properties. These properties are explained in terms of much stronger and large numbers of Si-N bonds in both the bulk of the dielectric films an in Si-SiO2 interface region.
KEYWORDS: Oxides, Monte Carlo methods, Integrated circuits, Semiconducting wafers, Integrated circuit design, Device simulation, Transistors, Metrology, Yield improvement, Process control
As an extension to approaches in wafer processing, a new technique is being developed: Dynamic Design Processing. This technique is based on the recalculation of design specifications, whenever the results of any process step diverge specifications. These random divergences are inherent in any processing step. Recalculation of the design specification values restores the final performance of the device to the desired one. Simulation results show that applying this technique is practically equivalent to eliminating the process randomness.
This paper briefly reviews techniques to assess and model ohmic contacts between layers with finite conductivity. It is then extended to consider aspects of these models that are applicable to multilayer structures such as those found in high electron mobility transistors [HEMTS] and provides electrical models for these structures. Experimental results are included in some instances to provide insight into the magnitude of the parameters of the models.
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