KEYWORDS: Global Positioning System, Data modeling, Education and training, Feature extraction, Modeling, Simulation of CCA and DLA aggregates, Back end of line, Simulations, Machine learning, Design and modelling
BackgroundLine-end-pull-back (LEPB) is a well-known systematic defect in BEOL metal layers, where a line-end (LE) tip is pulled back from its desired location due to lithography (litho) process effects. Severe LEPB directly affects BEOL connectivity and may lead to partial or total metal-via disconnection.AimLEPB can be characterized through model-based litho simulations but at the cost of high computational resource consumption. This study aims to provide a fast and accurate approximation of computationally expensive litho simulations through regression-based machine learning (ML) modeling.ApproachLEPB modeling is approached through the LightGBM model. Input features were approached using density pixels, density concentric circle area sampling (CCAS), and geometrical positioning surveying (GPS), which is an edge-based engine that provides a direct one-to-one mapping between model features and geometrical measurements between the LE as a point-of-interest and its surrounding contextual patterns. The importance of LightGBM features by splits was employed to reduce features across the used approaches.ResultsThe reduced features of GPS produced almost the same modeling quality (training: RMS = 0.571 nm, δEWD = 0.297 nm, and R2 % = 98.74 % , and testing: RMS = 0.643 nm, δEWD = 0.344 nm, and R2 % = 98.40 % ) with −22.22 % fewer number of features and less feature extraction runtime compared to the full features set of density pixels and density CCAS approaches.ConclusionsCompared to model-based litho simulations, the obtained calibrated ML models can be used to provide fast, yet accurate predictions of the amounts of pull-back or extensions introduced at LEs near vias, eliminating a major contributor to systematic IC yield loss.
As the semiconductor manufacturing technology node scales down in the deep submicron domain, hotspot detection becomes more challenging and geo-contextually dependent than ever before. The need to profile IC layout patterns based on geometrical commonalities becomes a significant demand either during IC layout design or manufacturing phases. Identified hotspots during the manufacturing phase are usually correlated to specific geometrical configurations sensitive to the lithography process or other manufacturing processes. Accordingly, identifying similar geometrical configurations is an important step toward locating potential hotspots. Once these hotspots are identified, their patterns can be provided to the router to avoid using these patterns and find other valid alternatives. Furthermore, in the IC design sign-off phase or Design Rules Check (DRC), layout profiling can identify patterns with high commonalities to these problematic patterns that potentially lead to a yield loss. In this paper, we introduce automated IC layout patterns topological profiling approach using Directional Geometrical Kernels (DGKs) to capture the context of patterns around a Point-Of-Interest (POI) in an IC layout, such as a hotspot. The DGKs pattern representation provides a direct one-to-one mapping with physical geometrical measurements centered by the POI and doesn’t need further feature extraction models or maps used by other pixelized gridded imagebased or density-based representations, which are both time and computational resources-consuming. The DGKs are decomposed into topological and dimensional components. This makes the mechanism of patterns topological profiling not in need of complex models and can be precisely fine controlled to produce adequate patterns profiling granularity that is not easily approached by other patterns profiling alternatives.
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