CD measurements of advanced 3D-NAND Staircase process require development of new approaches in CD metrology [1]. The current CD SEM Contact Analysis used for 3D-NAND assumes that process control could be provided through a set of geometric parameters defining the contact shape (i.e. parameters of contact shape elliptic fit such as equivalent contact top diameter (Top CD), equivalent contact bottom diameter (Bottom CD), ellipticity, minor, major axis). The limitation of this approach for process control of complex structures was considered, and a new approach based on Grey Level Analysis of contact features in SEM images was proposed. However, this analysis is not enough for controlling the complicated 3D-NAND Staircase formation process steps, as contact holes with same geometric parameters but different depths cannot be separated by traditional CD SEM metrology measurement procedure (Figures 1 and 2). Thus, traditional CD SEM approach needs revisiting in order to work in situations where process control requires analysis of sophisticated Grey Level uniformity distribution. We propose a novel approach combining traditional metrology with machine learning methods. The essence of this new approach is to combine Grey Level attributes and traditional CD measured geometric parameters of the feature, obtained by traditional CD metrology flow, in a classification scheme (Figures 2 and 3). The proposed approach was qualified at Micron site demonstrating ~98% purity classification results.
The proposed approach is generic and can be extended to a large variety of process control applications. Enhancing regular metrology flow with the capability to classify Etch process quality eliminates the need for the expensive and destructive cross-sectional SEM analysis. Furthermore, this method has a clear advantage during the early R&D phase of process development as it increases the usefulness of the in-line metrology tool while the process is still immature and unstable.
The growing demand for advanced DRAM technologies requires development of novel process control methodologies reflecting design rule shrinkage. The new challenges for CD SEM metrology of dense feature arrays of DRAM layers are widely considered in the literature and ITRS documents. In addition to traditional SEM metrology methods based on measurement of individual features, the development of novel measurement techniques is required for dense cell arrays at small nodes.[1-3] We considered a novel metrology of CDSEM Critical Dimension (CD) in dense arrays, formed as capacitors in advanced dynamic random-access memory (DRAM) layers. The proposed approach is based on traditional CDSEM metrology methodology with new developments providing flexibility, CD-style high precision, and large statistical sampling capabilities for advanced Statistical Process Control (SPC). The metrology challenge is solved through development of new algorithmic approaches for dense array measurements. The approach was validated on data simulation of extracting geometry (CD) parameters of actual DRAM cell structures and verified on real data.
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