In the manufacturing of CMOS devices, the golden standard for determining yield at various stages of production is electrical testing. This allows for the identification of failing devices or early yield failures before proceeding to subsequent steps. However, the failure of electrical tests can occur due to various reasons inherent to the structures of the devices. Additionally, a comprehensive analysis is necessary to ascertain the root cause of the failure mechanism once a device does not pass the electrical tests.
193i SAQP has allowed industry for continued BEOL metal pitch scaling, but as metal pitches become even tighter EUV SADP becomes an interesting alternative. In this context we have explored within our dual damascene 3ML test vehicles how the EUV SADP process compares to 193i SAQP for printing MP21 M2 lines. Our first EUV SADP results already show a better wafer CDU compared to our POR 193i SAQP process.
On-product overlay (OPO) is an important indicator of device yield. In this work, we show that stressed thin films used in semiconductor manufacturing can be an important contributor to OPO at multiple length scales. Depending on the stress level, film thickness, and the mask design, the overlay impact can be a few nanometers for the exposure of the next lithography layer. A predictive compact model based on pattern density is developed to accurately predict this overlay impact. The model is then verified using short-loop dual damascene wafers with stress split. The predictive model opens a new opportunity for model-based mask correction during optical proximity correction to increase the overlay margin for subsequent lithography exposures.
As technology nodes continue to scale down, maintaining roughness and defectivity during the pattern transfer becomes more challenging. For the smallest features, Metal-Organic Resists (MOR) are preferred due to their better selectivity than Chemically Amplified Resists (CAR). However, MORs are usually negative tone resists. Primarily based on defectivity reasons, dark field Extreme Ultraviolet (EUV) masks are strongly preferred over light field EUV masks. Therefore, the MOR resist is more suited for pillar patterning than hole patterning. The purpose of this paper is to show that exposing pillars with MOR and converting them into holes can yield better roughness and defectivity than patterning holes with CAR directly. A similar comparison is done for the tone reversal of lines and spaces. It is shown that the Local Critical Dimension Uniformity (LCDU) of holes and the Line Edge Roughness (LER) of lines/spaces are well conserved throughout the tone inversion process.
As conventional pitch scaling is saturating, scaling boosters such as buried power rail (BPR) [1-4] and its extension to backside power delivery (BSPDN) [5, 6] could provide 20% and 30% area gain [7], respectively. BPR can also help to improve SRAM design [8] and is a building block in novel architectures such as CFET [9, 10], for technology scaling beyond the 3 nm CMOS node. The two main features of BPR technology include: (i) the introduction of BPR metal within the fin module (fig. 1). Metal insertion in front-end-ofline (FEOL) has a risk of tool/wafer cross-contamination. Ensuring that BPR metal is fully encapsulated during contamination critical processes such as epitaxy, is therefore, essential. A proper choice of metal limits the risk of device performance/reliability degradation from metal diffusion & mechanical stress. (ii) The addition of VBPR via connections from M0A contact level to the BPR lines. Its challenges include high aspect ratio (AR) patterning, achieving low resistance (R) and reliable contact with BPR. This paper reports an overview of BPR/Via-to-BPR (VBPR) module development and metallization options at BPR and VBPR.
The goal of this work is to prepare process readiness towards High NA EUV lithography, by using 0.33NA exposures on
NXE3400B scanner. We focus on photoresists, underlayers and etch processes mitigation of P24nm Line Space patterns.
Etch transfer has been validated for Metal Oxide Resist (MOR). Furthermore, we investigate challenges to accelerate
Chemically Amplified Resist (CAR) P24nm Line Space processes. Also, here, promising patterning results have been
achieved. Thin film metrology-friendly methods like Atomic Force Microscopy (AFM) have been performed to
characterize and improve the CAR-based etch processes.
For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a 193i technology became challenging and expensive to push beyond the technology node for complex features that can be tackled in a simpler manner by the Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part of the high-volume manufacturing device landscape and it has reached a critical decision point where one can push further the single print on 0.33NA full field scanner or move to a EUV double patterning technology with more relaxed pitches to overcome current 0.33NA stochastic limits. In this work we have selected the 28nm pitch dense line-space (P28) as critical decision check point. We have looked at the 0.33NA EUV single print because it is more cost effective than 0.33NA EUV double patterning. In addition, we have conducted a process feasibility study as P28 in single print is close to the resolution limit of the 0.33NA EUV full field scanner. We present the process results on 28nm dense line-space patterning by using Inpria’s metal-oxide (MOx) EUV resist. We discuss the lithographic and etching process challenges by looking at resist sensitivity, unbiased line edge roughness (LER) and nano patterning failures after etching (AE), using broad band plasma (BBP) and e-beam (EB) defectivity inspection tools. To get further understanding on the P28 single patterning capability we have integrated the developed EUV MOx process in a relevant iN7 technology test vehicle by developing a full P28 metallization module with ruthenium. In such a way we were able to carry on electrical tests on metallized serpentine, fork-fork and tip-to-tip structures designed with a purpose of enabling further learning on pattern failures through electrical measurements. Finally, we conclude by showing the readiness of P28 single exposure using Inpria’s MOx process on a 0.33NA EUV full field scanner.
U. Halisdemir, F. Schleicher, D. J. Kim, B. Taudul, D. Lacour, W. S. Choi, M. Gallart, S. Boukari, G. Schmerber, V. Davesne, P. Panissod, D. Halley, H. Majjad, Y. Henry, B. Leconte, A. Boulard, D. Spor, N. Beyer, C. Kieber, E. Sternitzky, O. Cregut, M. Ziegler, F. Montaigne, J. Arabski, E. Beaurepaire, W. Jo, M. Alouani, P. Gilliot, M. Hehn, M. Bowen
The conservation of an electron’s spin and symmetry as it undergoes solid-state tunnelling within magnetic tunnel junctions (MTJs) is thought to be best understood using MgO-based MTJs1. Yet the very large experimental values of tunnelling magnetoresistance (TMR) that justify this perception are often associated with tunnelling barrier heights well below those suggested by the MgO optical band gap. This combination of high TMR and low RA-product, while spawning spin-transfer/spin-orbit torque experiments and considerable industrial interest, cannot be explained by standard theory. Noting the impact of a tunnel barrier’s altered stoichiometry on TMR2, we reconcile this 10+year-old contradiction between theory and experiment by considering the impact of the MgO barrier’s structural defects3–5. We find that the ground and excited states of oxygen vacancies can promote localized states within the band gap with differing electronic character. By setting symmetry- and temperature-dependent tunnelling barrier heights, they alter symmetry-polarized tunnelling and thus TMR. We will examine how annealing, depending on MgO growth conditions, can alter the nature of these localized states. This oxygen vacancy paradigm of inorganic tunnelling spintronics opens interesting perspectives into endowing the MTJ with additional functionalities, such as optically manipulating the MTJ’s spintronic response.
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