Novel mask absorber materials have been explored to improve EUV imaging performance which includes a variation of film thickness, refraction index n and the extinction coefficient k. A few promising mask absorber candidates were fabricated and evaluated using imec patterning on random logic via design with minimum pitch of 36nm. This study compares the lithography performance of low-n EUV masks with different reflectivity to our Ta-based EUV mask reference. The masks are designed with resolution enhancement techniques (RET) including source-mask optimization (SMO), optical proximity correction (OPC) and sub-resolution assist feature (SRAF) to achieve optimum mask to imaging performance. This work discusses the random logic via patterning benefits and limitations using different low-n EUV masks, along with the potential to extend the resolution of NA0.33 EUV lithography to random logic via designs down to 32nm pitch.
Transistor pitch scaling drives the evolution of chip design. The late arrival of EUV lithography prompted the adoption of multiple patterning using 193i to continue transistor scaling. To facilitate multiple patterning integration schemes, the 2D design style was abandoned and unidirectional design style became dominant. As transistor scaling continues further, the demand on routing resources can exceed their supply leading to routing congestion. Exploration on 1.5D or curvilinear routing to resolve higher Metal 2 usage was studied. Nowadays, EUV lithography re-introduced single patterning for the most advanced nodes. At the same time, Multi Beam Mask Writer (MBMW) enables true curvilinear masks. The use of curvilinear routing can potentially resolve routing congestion and more relax design rule check by combining EUV lithography and MBMW. This paper focuses on the challenges in optical proximity correction (OPC) on a design with curvilinear routing. Wafer data will be evaluated to assess quality. The target design is a D-flipflop using 2D and curvilinear features in a local interconnect layer to reduce the congestion. The base pitch of this design was scaled from 40nm to 32nm. The test design was then OPCed using Model Based OPC and Inverse Lithography Technique. Finally wafer data and process window analysis across the pitch range from different OPC variations will be revealed.
The new generation of 10nm node DRAM devices have now adopted EUV based patterning techniques. With further shrink in design rules, single exposure EUV processes will be pushed further using advanced photoresists and new mask types. However, in absence of high NA EUV lithography ready for high volume manufacturing (HVM) until at least 2025, acceptable local CD (critical dimensions) uniformity and yielding process windows at low exposure dose are a challenge for single exposure EUV. Further, for EUV implementation in sub-32nm pitch DRAM capacitator patterning applications, multi-patterning techniques must be explored. In this paper, EUV based double-patterning techniques have been demonstrated to pattern honeycomb array contact holes and pillars. The processing utilizes two EUV masks, using simple angled line space patterns. We have explored two different types of double patterning options: litho-freeze-litho-etch (LFLE) to pattern contact holes and litho-etch-lithoetch (LELE) to pattern pillars. In the absence of high NA EUV, these processing techniques are useful to pattern tight pitch (e.g., 32nm) contact holes/pillars for newer generations of DRAM devices. Another key objective of this paper is to present a set of metrology characterization methods to enable proper process optimizations.
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