The performance of overlay metrology as total measurement uncertainty, design rule compatibility, device correlation, and measurement accuracy has been challenged at the 2× nm node and below. The process impact on overlay metrology is becoming critical, and techniques to improve measurement accuracy become increasingly important. We present a methodology for improving the overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with the least process impacts and reliable accuracies. Using the quality metric, a calibration method, Archer self-calibration, is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as critical dimension–scanning electron microscopy data collected on a device correlated metrology hybrid target or by electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. We provide an example of such a case.
One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.
Overlay metrology performance as Total Measurement Uncertainty (TMU), design rule compatibility, device correlation and measurement accuracy are been challenged at 2x nm node and below. Process impact on overlay metrology becoming critical, and techniques to improve measurement accuracy becomes increasingly important. In this paper, we present an innovative methodology for improving overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with least process impacts and reliable accuracies. Using the quality metric, an innovative calibration method, ASC (Archer Self Calibration) is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as CDSEM data collected on DCM (Device Correlated Metrology) hybrid target or electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. In this paper we bring an example of such use case.
One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (OVL) targets and actual device overlay error. In this study, we introduce the concept of Device Correlated Metrology (DCM), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking CD-SEM (Critical Dimension – Scanning Electron Microscope) target. The hybrid OVL target is designed to accurately represent the process influence found on the real device. In the general case, the CD-SEM can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of CD-SEM measurement uncertainty. Direct OVL measurements by CD-SEM show excellent correlation with optical OVL measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based OVL metrology methods using AIM or AIMid OVL targets, and scatterometry-based overlay methods such as SCOL (Scatterometry OVL). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.
KEYWORDS: Overlay metrology, Semiconducting wafers, Image quality, Image processing, Error analysis, Data modeling, Control systems, Current controlled current source, Quality measurement, Binary data
Overlay continues to be one of the key challenges for lithography in semiconductor manufacturing, especially in
light of the accelerated pace of device node shrinks. This reality will be especially evident at 20nm node where
DPL and multi-layer overlay will require 4nm or less in overlay control across many critical layers in order to
meet device yield entitlements. The motivation for this paper is based on improving DPL overlay control in face
of the high complexity involved with multi-layer overlay requirements. For example, the DPL-2nd-litho layer
will need to achieve tight registration with the DPL-1st-litho layer, and at the same time, it will need to achieve
tight overlay to the reference-litho layer, which in some cases can also be a DPL layer. Of course, multi-level
overlay measurements are not new, but the combination of increased complexity of multi-DPL layers and
extremely challenging overlay specifications for 20nm node together will necessitate a better understanding of
multi-level overlay control, specifically in terms of root cause analysis of multi-layer related overlay errors and
appropriate techniques for improvement
In this paper, we start with the identification of specific overlay errors caused by multi-layer DPL processing on
full film stack product wafers. After validation of these findings with inter-lot and intra-lot controlled
experiments, we investigate different advanced control techniques to determine how to optimize overlay control
and minimize both intra-lot and inter-lot sources of error. A new approach to overlay data analysis will also be
introduced that combines empirical data with target image quality data to more accurately determine and better
explain the root cause error mechanism as well as provide effective strategies for improved overlay control.
We studied the effect of ArF resist shrinkage under electron bombardment during ebeam metrology and also the effect of resist shrinkage on the after etch CD. The traditional approach is to reduce the electron energy and dose to minimize resist shrinkage, often at the cost of reduced precision and image quality. We found that resist trimming by high-density plasma etcher (ion density about 1012cm-3) can improve the stability of resist under ebeam. Exposed to beams of 600V and 300V accelerating voltage, fresh photoresist CD shrinkage was reduced by ~70% and ~50% after resist trimming in the etcher. The effect of resist trimming is similar to that of e-beam curing. More interestingly, after etch and clean of the wafer, no difference in average CD value was found between area exposed to ebeam measurement and area that were not measured. This suggests that the resist trimming step in the normal etching process may overwhelm resist shrinkage effect caused by ebeam metrology. The implication is that the key selection criteria for stable ebeam metrology on ArF resist is a beam that produces consistent shrinkage, not minimum average shrinkage.
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