Semiconductor manufacturing’s full chip RET/OPC operations rely on the process models calibrated against metrology data collected from custom designed test structures. Physics-based compact models and machine learning models inherently carry the issue of model coverage often synonymous with calibration test pattern coverage. Therefore, process models frequently fail to predict unseen patterns within error tolerance. With the push for advanced technology node, such events can even occur after a node is declared HVM ready. Foundries have been combating the model coverage deficiency through costly model revisions, or expensive repair flows. There has always been the desire to have capability to screen and enhance compact model of potential coverage issue. In this paper, we use the machine learning clustering platform to learn the signatures of the model calibration test patterns and then compare them to the new design patterns in terms of feature vectors’ space correlated to model parameters’ space. The comparison provides not only the locations of the new patterns but also the similarity ranking with respect to the reference pattern, so that those patterns can be included and be further analyzed for better model coverage. These patterns are often suitable candidates to be included into new model calibration set. In this application, full chip capability is also essential besides the accuracy of the learning. The full-chip pattern check needs to be done quickly and efficiently; hence this technology could be adopted for new chip screening, highlighting areas worth paying extra attention to during inspection.
Automotive semiconductor products demand high reliability. The current process of performing electrical test after fab-out may not be sufficient for efficient reliability management. This paper proposes an AI solution for improving the reliability of automotive semiconductor products. The solution includes two unique concepts: fab-data augmentation (FDA) to estimate missing values using partially available measurement data during the fabrication process and real-time prediction of reliability using machine learning (ML) models. The ML model is also used to identify and rank critical process steps that impact reliability, and to predict the reliability of wafers in real time. This allows low reliability wafers to be screened out early during the chip fabrication process, improving the overall reliability of the final product.
Maximizing yield in a modern semiconductor fab requires proper optimization of the design (layout), process technology, and fab process tool recipes. For the past decade the prevalence of systematic defects tied to design or design-process interactions have predominated over random defect sources. Previously Resolution Enhancement Technology (RET), Design For Manufacturability (DFM), and Design-Technology Co-optimization (DTCO) techniques were the successful response to eliminating systematic yield limiting patterns. Machine learning, with its ability to find trends and make predictions based on large volumes of data, provides a unique path towards further reduction in systematic defect levels. This talk will present methods based on the use of design and process info with machine learning and computational lithography methods to identify and eliminate yield limiting patterns in the design, improve the accuracy of mask generation with etch and resist modeling and OPC, and improve the productivity and accuracy of fab defect detection and diagnostics. This paper will present methods to improve EPE control and reduce systematic hotspots through both supervised and unsupervised machine learning. Specifically we will focus on 3 areas: - identifying and yield limiting patterns in the design phase. - improving the accuracy (EPE control) of mask generation with machine learning assisted etch and resist modeling and OPC. - improving the productivity and accuracy of fab defect detection and diagnostics with machine learning.
Etch process is critical to CD control in patterning, but Etch-aware OPC is not as accurate as lithographyaware OPC. Etch process is not understood very well compared to lithography, so empirical etch model like Variable Etch Bias (VEB) has been used for OPC. Although VEB has been quite successful so far, accuracy of etch model needs be improved with below 10 nm node devices. Machine Learning (ML) is applied in this work for VEB model improvement. However, ML is also an extreme empirical model, in fact, so over-fitting is a big problem with machine learning. We demonstrate over-fitting as well as accuracy can be improved in this work as presenting specific methods of ML such as double-stage machine learning, etch-relevant inputs and ensuring sample-coverage.
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