IBM Research recently announced that 2nm node Nanosheet Technology is able to deliver superior density, power and performance compared to today’s 7nm FinFET technology in mass production. To enable 2nm node Nanosheet Technology, advanced patterning solutions are required. Dimensional compression drives the need for advanced patterning solutions including wider use of extreme ultraviolet (EUV) lithography. This also creates higher in feature aspect ratios, which in turn creates additional challenges during plasma etch. As aspect ratios continue to increase, difficulty with in-feature ion, radical, and volatile species transport during plasma etch presents an exceptional challenge. Dimensional scaling and wider use of EUV increases the need for further reduction of critical dimension (CD) variability, including line edge and line width roughness. The introduction of 3-dimensional gate all around nanosheet architecture has introduced an additional unique set of patterning challenges to address for coming technology nodes. When combined with dimensional scaling there is a clear need for novel advanced patterning process solutions to enable future nodes. In this presentation a variety of these challenges and the impact they will have on device and node scaling will be introduced and reviewed.
Emerging memory devices, such as MRAM, RRAM, and PCM, plays an important role in in-memory computation technology which can lead to significant acceleration for machine learning and AI applications.[1-3] The basic structure of these memory cell is simply a pillar made of a wide range of materials, however, the local CD uniformity (LCDU) of the pillars is especially crucial for these memory devices. The stringent LCDU requirement derives from either the intrinsic small resistance difference between the two memory states or the requirement for creating a large number of memory states within a small range of resistance. Apparently, the stochastic variation in physical dimension will correspond to the variation in resistance from cell to cell, which will affect the correct readout of the memory states and fail the device.
Because the “local” CDU in this context refers to the variation within the memory array, i.e. typically within several um, it is almost impossible to correct by utilizing existing advanced tools or process control techniques. In this work, we will demonstrate four promising options to address the stochastic effect in LCDU of pillars: a) adopting new resists, b) PTD and NTD shrink, c) DSA, d) cross-SADP. Fig. 1 shows the general approach to achieve better LCDU by printing larger CD at litho and shrink by post-litho processing.[4] Here we carefully characterize two shrinking techniques and its efficacy on LCDU improvement. Fig. 2 shows two alternative approaches, i.e. DSA and cross-SADP.[5] We will carefully explore these four approaches for LCDU improvement with thorough characterization and analysis. Subsequent pattern transfer and the retention of the LCDU improvement and cost/quality trade-off will also be discussed. Defectivity learning will also be discussed.
Extending extreme ultraviolet (EUV) single exposure patterning to its limits is dependent on eliminating its stochastic defectivity. Along with developments in photoresist platforms, the patterning film stack also needs to be considered. The material immediately underneath the photoresist is expected to have significant impact on both lithographic and pattern transfer performance. By designing the resist substrate interface with high EUV absorbance, there is potential to increase the EUV quantum yield of the exposure process. Increasing the selectivity to organic layer offers the opportunity to modulate stochastic defects through etch strategies. This paper will demonstrate the patterning of various chemically amplified resists on a high-Z metal-based hardmask. The potential for dose reduction, higher etch selectivity, and defectivity improvement from a high-Z hardmask will be discussed. Deposition-trim etch techniques will be used for decreasing the transfer of stochastic defects to the underlying substrate. Sub-32nm pitch trench patterning, defectivity, and electrical yield for this patterning stack will be highlighted.
Stochastic defects in the photoresist profile are one of the main yield limiters in EUV lithography patterning. These stochastic defects can be, for example, local resist loss, resist profile footing, or resist scumming. A subset of these defects is transferred through the hardmask open (HMO) patterning, leading ultimately to electrical opens and shorts. We use on-wafer data and process recipes to inform a physical etch model of the HMO process. This model is tested and confirmed by comparison to additional on-silicon data. The established model provides a visualization of the defect transfer through individual process steps and highlights critical patterning steps that may limit electrical yield. For example, a change in in-situ deposition time is observed to be more sensitive than oxide open or planarization film open times both in the model and on-wafer. This provides us the insight to focus tuning deposition step times to reduce defectivity and improve process performance. Furthermore, this model provides insight into the type of defects which are eliminated during specific patterning steps, and the type of defects which are persistent and ultimately lead to electrical opens and shorts. To characterize these defects, we plant intentional defects with varying dimensions and study which ones stay through the entire HMO process and which ones are eliminated. This insight helps better understand the HMO process, which may lead in the future to further process improvements.
Extending extreme ultraviolet (EUV) single exposure patterning to its limits is dependent on eliminating its stochastic defectivity. Along with developments in photoresist platforms, the patterning film stack also needs to be considered. The material immediately underneath the photoresist is expected to have significant impact on both lithographic and pattern transfer performance. By designing the resist substrate interface with high EUV absorbance, there is potential to increase the EUV quantum yield of the exposure process. This paper will demonstrate the patterning of a chemically amplified resist on a high-Z metal-based hardmask. The potential for dose reduction, higher etch selectivity, and defectivity improvement from a high-Z hardmask will be discussed. Deposition-trim etch techniques will be used for decreasing the transfer of stochastic defects to the underlying substrate. Sub-32nm pitch trench patterning, defectivity, and electrical yield for this patterning stack will be highlighted.
The thin nature of EUV (Extreme Ultraviolet) resist has posed significant challenges for etch processes. In particular, EUV patterning combined with conventional etch approaches suffers from loss of pattern fidelity in the form of line breaks. A typical conventional etch approach prevents the etch process from having sufficient resist margin to control the trench CD (Critical Dimension), minimize the LWR (Line Width Roughness), LER (Line Edge Roughness) and reduce the T2T (Tip-to-Tip). Pre-etch deposition increases the resist budget by adding additional material to the resist layer, thus enabling the etch process to explore a wider set of process parameters to achieve better pattern fidelity. Preliminary tests with pre-etch deposition resulted in blocked isolated trenches. In order to mitigate these effects, a cyclic deposition and etch technique is proposed. With optimization of deposition and etch cycle time as well as total number of cycles, it is possible to open the underlying layers with a beneficial over etch and simultaneously keep the isolated trenches open. This study compares the impact of no pre-etch deposition, one time deposition and cyclic deposition/etch techniques on 4 aspects: resist budget, isolated trench open, LWR/LER and T2T.
Current EUV lithography pushes photoresist thickness reduction to sub-30 nm in order to meet resolution targets and mitigate pattern collapse. In order to maintain the etch budgets in hard mask open, the adhesion layer in between resist and hard mask has to scale accordingly. We have reported a grafted polymer brush adhesion layer used in an ultrathin EUV patterning stack and demonstrated sub-36 nm pitch features with significant improvement over existing adhesion promotion techniques [1]. This paper provides further understanding of this class of materials from a fundamental point of view. We first propose a hypothesis of the adhesion mechanism, and probe key factors that could affect adhesion performance. The grafting kinetics study of polymer brush that contains different functional groups to the substrate shows grafting chemistry, time, and temperature are key factors that affect the printing performance. We then conduct a systematic study to understand printing capability at various pitches for different silicon-based substrates. By comparing the process window, we gain comprehensive understanding of the printing limits and failing modes with this approach. We provide a comparative study of a grafted adhesion layer vs. a conventional spin on BARC type material, including defectivity. Pattern transfer to hard mask with varied etch chemistry is conducted to understand the performance of polymer brush during etch.
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