Proceedings Article | 20 March 2020
KEYWORDS: Reliability, Inspection, Semiconducting wafers, Semiconductors, Defect inspection
Semiconductor reliability in applications such as automotive is getting increased attention as design rules shrink to include 1Xnm, semiconductor content per vehicle continues to grow, applications become more critical and reliability requirements tighten. Current automotive requirements stipulate less than one defective part per million (DPPM). Approaches to address reliability include improving design, manufacturing and test. Process control in manufacturing is critical for reliability and includes continuous improvement for reducing process tool defectivity, excursion monitoring of process tools and product lines, golden or best performing tool methods [1], measurement system analysis (MSA) methods and screening. Inline defectivity is known to have an impact on both yield and reliability [2], and defects can impact reliability in one of two ways. Killer defects located in areas that are untested can result in so called Zero- Kilometer failures. In other cases, the same types of defects that cause yield loss can also cause latent reliability failures – the difference being size, location and density. Latent reliability defects become activated after test and can include defect types such as partial bridges, partial opens, and embedded particles. Current reliability engineering relies on outlier detection rules like parametric part average testing (P-PAT) [3], or geographic part average testing (G-PAT), both of which are derived from end-of-line screening data, which is based solely on electrical test data [4]. Inline Part Average Testing (I-PAT™) is enabled by multi-channel high-speed LED scanning inspection technology and offers an opportunity to apply fab data to reliability engineering. Defect inspection results are analyzed with machine learning (ML) to weigh the defectivity and create a die-level defectivity metric allowing the statistical identification of die which are a high reliability risk [5, 6]. Two case studies are described. The first case is a feasibility study based on historical fab defectivity data and includes a sample of ~250,000 die, with eight inline defect inspections per wafer, including four front end of line (FEOL) and four back end of line (BEOL), on a high sensitivity broadband inspection system [7, 8]. Each defect is assigned a weight based on its impact to various “ground truth” indicators. The combined impact of all defects in a given die stacked across all inspections is aggregated into a die-level metric. Plotting the die-level I-PAT metrics for all the die as a Pareto chart allows outliers to be identified using accepted statistical methods [9]. I-PAT metrics can then be correlated to electrical wafer sort (EWS) yield or fallout rate, specific wafer-sort bins, EWS parametric test performance and post burn-in electrical test. Of key importance is that wafer test was not used to train the I-PAT model, and therefore this method is an independent validation of latent reliability. The second case study focuses on production screening feasibility with multi-channel high-speed LED scanning, and addresses overkill, or the over inking of potentially good die based on inline defectivity, which is a critical challenge that must be overcome for production implementation [10]. Using inspection enabled by high speed LED scanning technology, die screening is a critical component of a comprehensive automotive Zero Defect program. Applications include early detection of fab excursions, feedback for continuous improvement of inline defectivity, feedforward to optimize electrical test methods and screening of die containing possible latent reliability defects. The I-PAT methodology can be used to enhance standard end-of-line outlier detection rules such as P-PAT [3], which is based solely on parametric testing.
