KEYWORDS: Logic, Patents, Clocks, Data modeling, Computer architecture, Data storage, Control systems, Systems modeling, Very large scale integration, Computing systems
This report describes an open source VHDL description of a 64-bit MIPS-based processor. The pipeline can
execute most instructions from the MIPS III instruction set architecture (ISA). The full pipeline is made available
to digital VLSI engineers as a platform to test cell designs as a part of a complete computing system. The pipeline
is an 8-stage RISC based on the MIPS R4000 series of processors, and includes common arithmetic operations
on 32- and 64-bit operands, and full IEEE 754 floating point support. This report describes the architecture
and components of the MIPS-based processor.
Low density parity check decoders use computation nodes with multioperand adders on their critical path. This
paper describes the design of estimating multioperand adders to reduce the latency, power and area of these
nodes. The new estimating adders occasionally produce inaccurate results. The effect of these errors and the
subsequent trade-off between latency and decoder frame error rate is examined. For the decoder investigated it
is found that the estimating adders do not degrade the frame error rate.
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