Most advanced wafer fabs have embraced complex pattern decoration, which creates numerous challenges during in-fab reticle qualification. These optical proximity correction (OPC) techniques create assist features that tend to be very close in size and shape to the main patterns as seen in Figure 1. A small defect on an assist feature will most likely have little or no impact on the fidelity of the wafer image, whereas the same defect on a main feature could significantly decrease device functionality. In order to properly disposition these defects, reticle inspection technicians need an efficient method that automatically separates main from assist features and predicts the resulting defect impact on the wafer image. Analysis System (ADAS) defect simulation system[1]. Up until now, using ADAS simulation was limited to engineers due to the complexity of the settings that need to be manually entered in order to create an accurate result. A single error in entering one of these values can cause erroneous results, therefore full automation is necessary. In this study, we propose a new method where all needed simulation parameters are automatically loaded into ADAS. This is accomplished in two parts. First we have created a scanner parameter database that is automatically identified from mask product and level names. Second, we automatically determine the appropriate simulation printability threshold by using a new reference image (provided by the inspection tool) that contains a known measured value of the reticle critical dimension (CD). This new method automatically loads the correct scanner conditions, sets the appropriate simulation threshold, and automatically measures the percentage of CD change caused by the defect. This streamlines qualification and reduces the number of reticles being put on hold, waiting for engineer review. We also present data showing the consistency and reliability of the new method, along with the impact on the efficiency of in-fab reticle qualification.
Even small defects on the main patterns can create killer defects on the wafer, whereas the same defect on or near the decorative patterns may be completely benign to the wafer functionality. This ambiguity often causes operators and engineers to put a mask "on hold" to be analyzed by an AIMS™ tool which slows the manufacturing time and increases mask cost. In order to streamline the process, mask shops need a reliable way to quickly identify the wafer impact of defects during mask inspection review reducing the number of defects requiring AIMS™ analysis.
Source Mask Optimization (SMO) techniques are now common on sub 20nm node critical reticle patterns These techniques create complex reticle patterns which often makes it difficult for inspection tool operators to identify the desired wafer pattern from the surrounding nonprinting patterns in advanced masks such as SMO, Inverse Lithography Technology (ILT), Negative Tone Development (NTD).
In this study, we have tested a system that generates aerial simulation images directly from the inspection tool images. The resulting defect dispositions from a program defect test mask along with numerous production mask defects have been compared to the dispositions attained from AIMS™ analysis. The results of our comparisons are presented, as well as the impact to mask shop productivity.
IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly
for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically
remain in the “requal” phase for extended, non-productive periods of time. The overall “requal” cycle time in which
reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold
until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles
can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields.
One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects.
Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each
additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects.
Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding
lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due
to lithographic uncertainty presents significant cycle time loss and increased production costs
An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved
to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect’s printability
under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm
node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the
results of both AIMS optical simulation and to actual wafer prints.
Advanced IC fabs must inspect critical reticles on a frequent basis to ensure high wafer yields. These necessary requalification inspections have traditionally carried high risk and expense. Manually reviewing sometimes hundreds of potentially yield-limiting detections is a very high-risk activity due to the likelihood of human error; the worst of which is the accidental passing of a real, yield-limiting defect. Painfully high cost is incurred as a result, but high cost is also realized on a daily basis while reticles are being manually classified on inspection tools since these tools often remain in a non-productive state during classification. An automatic defect analysis system (ADAS) has been implemented at a 20nm node wafer fab to automate reticle defect classification by simulating each defect’s printability under the intended illumination conditions. In this paper, we have studied and present results showing the positive impact that an automated reticle defect classification system has on the reticle requalification process; specifically to defect classification speed and accuracy. To verify accuracy, detected defects of interest were analyzed with lithographic simulation software and compared to the results of both AIMS™ optical simulation and to actual wafer prints.
IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification
inspections are costly for many reasons including the capital equipment, system maintenance, and
labor costs. In addition, masks typically remain in the “requal” phase for extended, non-productive
periods of time. The overall “requal” cycle time in which reticles remain non-productive is
challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master
critical layer reticle is returned to production. Unfortunately, substituting backup critical layer
reticles can significantly reduce an otherwise tightly controlled process window adversely affecting
wafer yields.
One major requal cycle time component is the disposition process of mask inspections containing
hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of
potentially yield-limiting detections, each additional classification increases the risk of manual
review techniques accidentally passing real yield limiting defects. Even assuming all defects of
interest are flagged by operators, how can any person's judgment be confident regarding lithographic
impact of such defects? The time reticles spend away from scanners combined with potential yield
loss due to lithographic uncertainty presents significant cycle time loss and increased production
costs.
Fortunately, a software program has been developed which automates defect classification with
simulated printability measurement greatly reducing requal cycle time and improving overall
disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in
both engineering and high-volume production environments with very successful results. In this
paper, data is presented supporting significant reduction for costly wafer print checks, improved
inspection area productivity, and minimized risk of misclassified yield limiting defects.
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