Stress technologies such as stress liners are used to improve the performance of advanced CMOS devices. Due to the contextual situation of a transistor in the physical design layout, unintended stress from neighboring cells can cause variations in the transistor characteristics. This effect is called Layout Dependent Effect (LDE). In this work we propose a fast method to detect outlier transistors due to the LDEs by profiling and sampling them from the VLSI design with millions of transistors and many devices. The proposed method can reduce the TAT for quantitative evaluation of the LDE for design layouts that have not passed the LVS. We also propose a pattern matching based method to search motifs created by encapsulating neighborhood of outlier transistors with large Vth variations. This enables designers to trace such LDE hotspot patterns and thereby outlier transistors during the design phase.
Recently, Ising machines, which solve Quadratic Unconstrained Binary Optimization (QUBO) problems in a short computation time, have attracted attention. In this paper, we propose a mask optimization method using an Ising machine to obtain a mask with high fidelity to target patterns and high tolerance to process variation. In the proposed method, a mask pattern is improved by repeatedly solving QUBO problems by the Ising machine. In experiments, we applied the proposed method using the Ising machine to various patterns and evaluated it in comparison with existing methods in fidelity to target patterns, tolerance to process variation, and execution time.
KEYWORDS: Feature extraction, Feature selection, Lithography, Simulation of CCA and DLA aggregates, Machine learning, Manufacturing, Computer programming, Semiconducting wafers, Design for manufacturability, Very large scale integration
As VLSI device feature sizes are getting smaller and smaller, lithography hotspot detection and elimination have become more important to avoid yield loss. Although various machine learning based methods have been proposed, it is not easy to find appropriate parameters to achieve high accuracy. This paper proposes a feature selection method by using the probability distributions of layout features. Our method enables automatic feature optimization and classifier construction. It can be adaptive to different layout patterns with various features. In order to evaluate hotspot detection methods in the situation close to actual problem, dataset based on ICCAD2019 dataset is used for evaluation. Experimental results show the effectiveness of our method and limitations.
As one of Resolution Enhancement Techniques, a mask optimization such as Pixel-based Optical Proximity Correction or Inverse Lithography Technology is well discussed. In this paper, a pixel-based mask optimization using 0-1 Quadratic Programming problem (0-1 QP) is proposed to obtain enough image contour fidelity and tolerance to process variation in a short time. By formulating 0-1 QP to maximize intensity slope around between edges of target patterns, suppression of image contour distortion by the process variation is realized. The defined 0-1 QP is relaxed into Lagrangian relaxation problem and an approximate solution of the defined 0-1 QP is obtained by solving Lagrangian relaxation problem by using Subgradient method and gradient deciding method. Moreover, by applying a correction method which corrects boundary pixel of target patterns precisely into the mask obtained by 0-1 QP, enough shape fidelity toward target patterns can be obtained.
LELECUT type triple patterning lithography is one of the most promising techniques in 14 nm logic node and beyond. To prevent yield loss caused by overlay error, LELECUT mask assignment, which is tolerant to overlay error, is desired. We propose a method that obtains a LELECUT assignment that is tolerant to overlay error. The proposed method uses positive semidefinite relaxation and randomized rounding technique. In our method, the cost function that takes the length of boundary of features determined by the cut mask into account is introduced.
Self-Aligned Quadruple Patterning (SAQP) will be one of the leading candidates for sub-14nm node and beyond. However, compared with triple patterning, making a feasible standard cell placement has following problems. (1) When coloring conflicts occur between two adjoining cells, they may not be solved easily since SAQP layout has stronger coloring constraints. (2) SAQP layout cannot use stitch to solve coloring conflict. In this paper, we present a framework of SAQP-aware standard cell placement considering the above problems. When standard cell is placed, the proposed method tries to solve coloring conflicts between two cells by exchanging two of three colors. If some conflicts remain between adjoining cells, dummy space will be inserted to keep coloring constraints of SAQP. We show some examples to confirm effectiveness of the proposed framework. To our best knowledge, this is the first framework of SAQP-aware standard cell placement.
LELECUT type triple patterning lithography is one of the most promising techniques in the next generation lithography. To prevent yield loss caused by overlay error, LELECUT mask assignment which is tolerant to overlay error is desired. In this paper, we propose a method that obtains an LELECUT assignment which is tolerant to overlay error. The proposed method uses positive semide_nite relaxation and randomized rounding technique. In our method, the cost function that takes the length of boundary of features determined by the cut mask into account is introduced.
Litho-Etch-Litho-Etch (LELE) type double patterning technology (DPT) is known to have an advantage of layout flexibility. However, there are two problems when a hotspot, which is not fixable by tuning OPC, is detected. One is repeating a data preparation flow including decomposition, OPC, and verification by lithography simulation is quite time consuming. The other is a risk to introduce new hotspots at different locations. In this report, a new method to fix hotspots with layout modification of limited area will be presented. The proposed method can reduce not only turnaround time to fix a hotspot but also the number of iterations since it prevents generation of hotspots at new locations.
Self-Aligned Quadruple Patterning (SAQP) is one of the most leading techniques in 14 nm node and beyond. However, the construction of feasible layout configurations must follow stricter constraints than in LELELE triple patterning process. Some SAQP layout decomposition methods were recently proposed. However, due to strict constraints required for feasible SAQP layout, the decomposition strategy considering an arbitrary layout does not seem realistic. In this paper, we propose a new routing method for feasible SAQP layout requiring no decomposition. Our method performs detailed routing by correct-by-construction approach and offers compliant layout configuration without any pitch conflict.
In this paper, we propose a fast layout decomposition algorithm in litho-etch-litho-etch (LELE) type double patterning considering the yield. Our proposed algorithm extracts stitch candidates properly from complex layouts including various patterns, line widths and pitches. The planarity of the conflict graph and independence of stitch-candidates are utilized to obtain a layout decomposition with minimum cost efficiently for higher yield. The validity of our proposed algorithm is confirmed by using benchmark layout patterns used in literatures as well as layout patterns generated to fit the target manufacturing technologies as much as possible. In our experiments, our proposed algorithm is 7.7 times faster than an existing method on average.
In this paper, we propose a new flexible routing method for Self-Aligned Double Patterning (SADP). SADP is one of the most promising candidates for patterning sub-20 nm node advanced technology but wafer images must satisfy tighter constraints than litho-etch-litho-etch process. Previous SADP routing methods require strict constraints induced from the relation between mandrel and trim patterns, so design freedom is unexpectedly lost. Also these methods assume to form narrow patterns by trimming process without consideration of resolution limit of optical lithography. The proposed method realizes flexible SADP routing with dynamic coloring requiring no decomposition to extract mandrel patterns and no worries about coloring conflicts. The proposed method uses realizable trimming process only for insulation of patterns. The effectiveness of the proposed method is confirmed in the experimental comparisons.
Self-Aligned Double Patterning (SADP) has become one of the most promising processes for 20nm node technology and
beyond. Despite its robustness against overlay, it is a challenging process for designers since predicting the wafer image
instantly is almost impossible. Self-Aligned Quadruple Patterning (SAQP) is also critical technology for sub-10nm
process but more complex than SADP, so it is too difficult to design a layout intuitively. Needless to say designing
layout by applying N times sidewalls intuitively is impossible for almost everyone. In this paper, we clarify a new
intuitive principle for SADP layout. The principle uses "Base patterns" painted in different two colors interchangeably.
The proposed method enables us to design SADP layout simply by connecting and cutting fundamental pattern
arbitrarily with a few restrictions. Another benefit is that either of two colors in the pattern can be used as mandrel. We
can apply the principle to not only SAQP but also N times sidewall processes. Considering these advantages, layout
formed by sidewall process becomes designer-friendly.
KEYWORDS: Lithography, Data storage, Optical proximity correction, Microelectronics, Design for manufacturability, Current controlled current source, Intellectual property, Time metrology
Layout verification is essential in the cutting-edge generation. Generally, it uses a lithography simulation (Lithography
Compliance Check: LCC) and requires a lot of calculation time. In order to reduce LCC time, we propose a clean pattern
matching method by means of a "clean pattern library". The proposed method searches for patterns without hotspots
(clean patterns) which usually occupy the most of the chip area. The conventional hotspot pattern matching method has
no guarantee that unmatched area is hotspot-free, so LCC is usually applied to the unmatched area. On the other hand,
the proposed matching method searches for "clean" patterns so that most of the area need not to be verified. As a result,
LCC time can be reduced. This paper shows the detailed flow of the proposed matching method. We present the
experimental results of layout verification in our 40nm system LSI designs and the effectiveness of the proposed method
is confirmed.
We have developed the comprehensive sub-resolution assist features (SRAFs) generation method based upon the
modulation of the coherence map. The method has broken through the trade-off relation between processing time and
accuracy of the SRAF generation. We have applied this method to a real device layout and the average of Process
Variation band width (PV band width) has improved to 40% without any processing time loss.
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