This paper presents the challenges in the high-frequency noise characterization and modeling of sub-100nm MOSFETs
for radio-frequency (RF) integrated circuits (IC). In general, it addresses three major issues - accuracy of high-frequency
(HF) noise measurements, impact of test structure designs and physics-based noise models for the noise sources of interest
- channel noise, induced gate noise and gate tunneling noise. In the first section, different HF measurement techniques,
namely Y-factor method and power-equation method are reviewed. The impact due to the difference in the output
impedances of a noise source in the hot and the cold states on the measurement accuracy is demonstrated. In the second
section, different test structures and de-embedding procedures for noise and scattering parameter de-embedding to get rid
of the parasitic effects from the probe pads and interconnections in a device-under-test (DUT) are reviewed. Special
considerations on the measurement accuracy are paid to the shift of DC bias conditions. Finally, with the power spectral
densities for the noise sources of interest obtained from the intrinsic noise parameters, different physics-based noise
models for these noise sources in sub-100nm MOSFETs are discussed. The impact of the channel-length modulation
(CLM) effect, the hot electron effect and the velocity saturation effect on the channel thermal noise and the impact of the
gate tunneling noise on the noise performance of deep submicron MOSFETs are reviewed.
KEYWORDS: Field effect transistors, Instrument modeling, Transistors, Resistance, Modulation, Metals, Lab on a chip, Scattering, Signal to noise ratio, Diffusion
This paper presents a thorough description of the high-frequency noise characterization and modeling of CMOS transistors for radio frequency (RF) integrated circuit (IC) design. It covers two main topics: high-frequency noise characterization and physics-based noise models. In the first section, two de-embedding procedures are presented for noise and scattering parameter de-embedding to get rid of the parasitic effects from the probe pads and interconnections in the device-under-test (DUT). With the intrinsic noise parameters, two extraction methods to obtain the channel noise, induced gate noise and their correlation in MOSFETs are discussed and experimental results are presented. Based on the noise information obtained in the first section, the second part of the paper presents physics-based noise models for the noise sources of interest in deep submicron MOSFETs. It discusses the model derivation, channel noise enhancement in deep submicron MOSFETs and impact of channel length modulation (CLM) effect. Finally a simple and accurate analytical model for channel noise calculation will be presented.
This paper reviews and also discusses some of the important issues in MOSFET Modeling for radio frequency integrated circuits (RFICs). A brief review of some popular or common MOSFET models that can predict the RF properties of MOSFETs is presented. At present, these include BSIM3v3, EKV, MOS Model 9 and adaptations of HSPICE models, and most of them are discussed here. Attention is paid to RF noise parameter extraction and modeling of MOSFETs, since this has been relatively neglected compared to the AC modeling and parameter extraction. Finally, some new and exciting result son the effects of DC electrical stresses on the microwave properties of NMOSFETs, especially the unity current-gain frequencies and maximum oscillation frequencies are presented for different stress times and at different biasing conditions. Modeling of the effects of stress on the RF properties of MOSFETs is still to be investigated.
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