Mr. Beom-Seok Seo Profile

Beom-Seok Seo

at SAMSUNG Electronics Co Ltd

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Publications (5)

Proceedings Article | 4 March 2010 Paper

Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows

Myung-Soo Noh, Beom-Seok Seo, Suk-Joo Lee, Alex Miloslavsky, Christopher Cork, Levi Barnes, Kevin Lucas

Proceedings Volume 7640, 76400S (2010) https://doi.org/10.1117/12.848194

KEYWORDS: Double patterning technology, Optical lithography, Photomasks, Logic, Product engineering, Parallel processing, Electronics, 193nm lithography, Electronic design automation, Resolution enhancement technologies

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Proceedings Article | 4 March 2010 Paper

Optical proximity correction enhancement by using model based fragmentation approaches

Young-Seok Woo, Woon-Hyuk Choi, Beom-Seok Seo, Yoo-Hyon Kim, Vladislav Liubich, Shady Abdelwahed, Juhwan Kim, James Word, Jong-Won Lee

Proceedings Volume 7640, 76401F (2010) https://doi.org/10.1117/12.848447

KEYWORDS: Optical proximity correction, Lithography, Optical lithography, Critical dimension metrology, Bridges, Resolution enhancement technologies, Semiconducting wafers, Lithographic illumination, Tolerancing, Computer simulations

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Proceedings Article | 11 May 2009 Paper

Double patterning addressing imaging challenges for near- and sub-k1=0.25 node layouts

Beom-Seok Seo, Dae-Kwon Kang, Myung-Soo Noh, Sung-Ho Lee, Christopher Cork, Gerald LukPat, Alexander Miloslavsky, Xiaohai Li, Kevin Lucas, Sooryong Lee

Proceedings Volume 7379, 73791N (2009) https://doi.org/10.1117/12.824300

KEYWORDS: Double patterning technology, Optical proximity correction, Silicon, Optical lithography, Photomasks, Logic, Etching, Manufacturing, Metals, Lithography

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A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to define critical layers with double photolithography and etch process becomes increasingly evident. Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D features is so challenging that opposing line-ends can only be defined using an additional litho and etch step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit. Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and then successfully decomposed, so an additional set of restrictions is required to make layouts double patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that they can be patterned using both masks. The electric performance of this cut circuitry may be highly dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to misalignment between the two patterning steps. We used representative logic layouts of metal level and realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned using double patterning aware OPC and printability verification tools.

Proceedings Article | 19 May 2008 Paper

A new approach to the DFM for the metals

No-Young Chung, Hee-Sang Bae, Beum-Seok Seo, Sung-Ho Lee, Sung-Il Kim, Sun-Yong Lee

Proceedings Volume 7028, 70283D (2008) https://doi.org/10.1117/12.793121

KEYWORDS: Process modeling, Design for manufacturing, Metals, 3D modeling, Optical lithography, Bridges, Optical proximity correction, Calibration, Optimization (mathematics), Etching

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Metal layers have some drawbacks in building up model based OPC (MBOPC) because metal layers are mainly composed of 2 dimensional (2D) patterns which show modeling inaccuracy and the difficulty of fragment optimization compared with 1-dimensional patterns. As a result, metal layers have considerable hot spots such as pinch, bridge and insufficient contact overlap. The modeling inaccuracy of 2D patterns results from a few reasons like measurement noise, inaccurate optical simulation and empirical resist modeling etc. The fragment optimization operated by rule does not control automatically corner rounding problems induced by small jogs of 2D patterns. The design for manufacturability (DFM) is known to provide a solution to overcome these problems. One of engines operating the DFM is MBOPC, which is made by an empirical process model and offers the process variation counter map simulated by the MBOPC engine. However, the accuracy of the simulation is quite low because we cannot avoid over-corrected patterns generated inevitably with the empirical model. In order to detect and correct the hot spots caused by the design itself, that is, the inherent function of the DFM, it is necessary to provide the OPC engine of the physical model with the optimized illumination condition to rule out empirical effect. Physical model is more emphasized in case of process window simulation because of its accuracy in the edge boundary of process window. One of important function of DFM for the metal layers is to enhance the contact overlap margin which can be influenced by the lithography process such as line end shortening, corner rounding effect and miss-alignment. Etch process is also a significant parameter of contact overlap. Calibrated process model is very effective to detect the insufficient contact overlap with process window. In this paper, MBOPC of sub-45nm node metal layers is studied to provide the effective DFM engine. The DFM flow with renewed MBOPC engine will show the improved process window and large contact overlap margin and will also make it possible to search and correct just patterns capable of decreasing the process window by only layout defect itself.

Proceedings Article | 21 March 2007 Paper

Lithography enhanced manufacturability analysis by using multilevel simulated contours

Beom-Seok Seo, Woon-Hyuk Choi, Jong-Woon Park, Soung-Su Woo, Sung-Ho Lee

Proceedings Volume 6521, 65210Y (2007) https://doi.org/10.1117/12.711825

KEYWORDS: Optical proximity correction, Diffusion, Lithography, Resolution enhancement technologies, Manufacturing, Critical dimension metrology, Logic, Design for manufacturability, Photomasks, Electroluminescence

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