Proceedings Article | 21 March 2007
KEYWORDS: Metals, Capacitance, System on a chip, Capacitive coupling, Tolerancing, Dielectrics, Intelligent sensors, Resistors, Field effect transistors, Capacitors
Distribution of mask pattern density of isolating or conducting, layers of the die, such as active, poly, or metals, impacts
product voltage tolerance and frequency response. At active level, nonuniform pattern density lowers punch-through or
breakdown voltages. At metal levels, planarity issues give rise to high via resistances and variations of inter-layer
capacitive coupling. Devices required to build an SoC product such as precision resistors, inductors, RF FETs, and
capacitors, have diversified geometry characteristics. Usually, the differences in pattern density they cause over the die
cannot be mitigated at design stage. Therefore, die pattern density has to be made uniform at die integration stage, by
global addition of fill features (waffles). This presents significant challenge as the criteria for this addition are often
contradictory or difficult to meet. The basic, but time consuming way of equalizing pattern density calls for manual
adding of dummy features. In comparison, a simplistic, automated geometric approach is to add fill pattern of fixed
density, which would then become target pattern density of the die. However, it may not be possible to equalize pattern
density over all the regions even allowing for some changes in the die architecture in the course of either manual or
automated waffling process. In addition, the approach tends to add dummy features even if unnecessary, creating local
extremes of pattern density. Such outcome is not always preferred by the product RF/analog applications, which can be
compromised by capacitive coupling through the waffles. In our methodology proposed in this work, the die pattern
density is first analyzed, followed by the adjustable, intelligent fill of dynamic density. This way, it is possible to keep
the original pattern density and work only on the areas of small density. We also propose to adjust the standard cell
methodology in order to enable pre-die level modifications of pattern density and its extraction and ensure that all the
required blocks could be placed on the product with their parasitics accounted for.
