In this paper we show experimental verification of the feasibility of printing pitch 40x70nm hexagonal holes using EUV single patterning. We show that at a local CDU (LCDU) of 2.7nm and an exposure dose of 54 mJ/cm2 a defect rate smaller than 7x10-9 is observed. This result was enabled by optimization of the illumination source and improvements in the resist. Resist selection identified multiple candidates that show a promising LCDU performance and optimization of the processing conditions resulted in improved performance. Experimental validation of the defect performance was done using HMI eP5 on the baseline process. Assessment of the LCDU performance for EUV single expose at pitches beyond 40x70nm, showed promising results.
After an initial introduction into logic fabrication, EUV lithography is finally moving into memory fabrication, and now memory companies must untangle the complex physics required to create an aerial image with this next generation technology. The optical proximity correction (OPC) model must understand and compensate for new EUV phenomena, such as non-telecentric illumination induced shadowing, across-slit variation, optical flare, and reticle black border effects. This paper compares the EUV OPC Modeling flow with the DUV modeling flow and discusses the new challenges EUV presents to OPC Model building for high-volume manufacturing.
Block copolymer directed self-assembly (BCP-DSA) may provide a less costly method of forming sub-38nm pitch line-space patterns relative to proven HVM methods, but DSA needs to provide equivalent or improved defect density and pattern quality to warrant consideration for displacing current HVM methods. This paper evaluates the process constraints of three DSA flows and compares the pattern quality after pattern transfer for each flow at its optimal process conditions to the same pattern created by a proven HVM process flow.
Although extreme ultraviolet lithography (EUVL) remains a promising candidate for semiconductor device manufacturing of the 1× nm half pitch node and beyond, many technological burdens have to be overcome. The “field edge effect” in EUVL is one of them. The image border region of an EUV mask, also known as the “black border” (BB), reflects a few percent of the incident EUV light, resulting in a leakage of light into neighboring exposure fields, especially at the corner of the field where three adjacent exposures take place. This effect significantly impacts on critical dimension (CD) uniformity (CDU) across the exposure field. To avoid this phenomenon, a light-shielding border is introduced by etching away the entire absorber and multilayer at the image border region of the EUV mask. We present a method of modeling the field edge effect (also called the BB effect) by using rigorous lithography simulation with a calibrated resist model. An additional “flare level” at the field edge is introduced on top of the exposure tool flare map to account for the BB effect. The parameters in this model include the reflectivity and the width of the BB, which are mainly determining the leakage of EUV light and its influence range, respectively. Another parameter is the transition width which represents the half shadow effect of the reticle masking blades. By setting the corresponding parameters, the simulation results match well the experimental results obtained at the IMEC’s NXE:3100 EUV exposure tool. Moreover, these results indicate that the out-of-band (OoB) radiation also contributes to the CDU. Using simulation, we can also determine the OoB effect rigorously using the methodology of an “effective mask blank.” The study demonstrates that the impact of BB and OoB effects on CDU can be well predicted by simulations.
As EUV Lithography (EUVL) continues to evolve, it offers a possible solution to the problems of additional masks
and lithography steps that drive up the cost and complexity of 193i multiple patterning. EUVL requires a non-telecentric
reflective optical system for operation. This requirement causes EUV specific effects such as shadowing. The absorber
physically shadows the reflective multilayer (ML) on an EUV reticle resulting in pattern fidelity degradation. To reduce
this degradation, a thinner absorber may help. Yet, as the absorber thickness decreases, reflectivity increases in the ‘dark’
region around the image field, resulting in a loss of contrast. The region around the edge of the die on the mask of unpatterned
absorber material deposited on top of ML, known as the image border, is also susceptible to undesirable
reflections in an ideally dark region. For EUVL to be enabled for high-volume manufacturing (HVM), reticle masking
(REMA) blades are used to shield light from the image border to allow for the printing of densely spaced die. When die
are printed densely, the image border of each neighboring die will overlap with the edge of a given die resulting in an
increase of dose that overexposes features at the edge of the field. This effect is convolved with a fingerprint from the
edge of the REMA blades. This phenomenon will be referred to as a field edge effect.
One such mitigation strategy that has been investigated to reduce the field edge effect is to fully remove the ML
along the image border to ensure that no actinic-EUV radiation can be reflected onto neighboring die. This has proven to
suppress the effect, but residual out-of-band radiation still provides additional dose to features near the image border,
especially in the corners where three neighboring fields overlap. Measurements of dense contact holes (CHs) have been
made along the image border with and without a ML-etched border at IMEC in collaboration with Micron using the
ASML NXE:3100. The implementation of these measurements allow for further mitigation, i.e., compensation by OPC.
Mentor Graphics’ Calibre software uses the scanner’s point spread function and convolves it with the mask layout to
generate a flare map. It also has the capability to add additional dose to the image border which can be optimized to fit
the experimental data. This includes the transition region between the image field and border that results in a linear rolloff
of dose due to partial shadowing of the REMA blades. By applying this flaremap that accounts for neighboring die to
the already calibrated optical and resist models, OPC can now be enabled to compensate for field edge effects.
This study has two goals. First, we will show that OPC can be used to compensate both for field edge effects with
and without a etched ML border. The second is to investigate the limitations that exist for OPC in the areas altered by
neighboring die. This will predict when a process to mitigate the field edge effect is needed to enable EUV HVM.
Block co-polymer directed self-assembly (BCP DSA) has become an area of fervent research activity as a potential alternative or adjunct to EUV lithography or self-aligned pitch multiplication strategies. This presentation will evaluate two DSA strategies for patterning line-space arrays at 30nm pitch: graphoepitaxial DSA with surface-parallel cylinder BCPs and chemoepitaxial DSA with surface-normal lamellar BCPs. A comparison of pattern transfer into hard-mask and substrate films will be made by consideration of line and space CDs, line profile of cross-sectional SEM images, and comparison of relative LWR/SWR. The processes will be benchmarked against Micron’s process used in manufacturing its 16nm half-pitch NAND part.
Although extreme ultraviolet lithography (EUVL) remains a promising candidate for semiconductor
device manufacturing of the 1x nm half pitch node and beyond, many technological burdens have to
be overcome. The “field edge effect” in EUVL is one of them. The image border region of an EUV
mask,also known as the “black border” (BB), reflects a few percent of the incident EUV light,
resulting in a leakage of light into neighboring exposure fields, especially at the corner of the field
where three adjacent exposures take place. This effect significantly impacts on CD uniformity
(CDU) across the exposure field. To avoid this phenomenon, a light-shielding border is introduced
by etching away the entire absorber and multi-layer (ML)at the image border region of the EUV
mask. In this paper, we present a method of modeling the field edge effect (also called the BB effect)
by using rigorous lithography simulation with a calibrated resist model. An additional “flare level”
at the field edge is introduced on top of the exposure tool flare map to account for the BB effect. The
parameters in this model include the reflectivity and the width of the BB, which are mainly
determining the leakage of EUV light and its influence range, respectively. Another parameter is the
transition width which represents the half shadow effect of the reticle masking blades. By setting the
corresponding parameters, the simulation results match well the experimental results obtained at the
imec’s NXE:3100 EUV exposure tool. Moreover, these results indicate that the out-of-band (OoB)
radiation also contributes to the CDU. Using simulation we can also determine the OoB effect
rigorouslyusing the methodology of an “effective mask blank”. The study in this paper demonstrates
that the impact of BB and OoB effects on CDU can be well predicted by simulations.
For device manufacturing at the 10nm node (N10) and below, EUV lithography is one of the technology options to
achieve the required resolution. Besides high throughput and extreme resolution, excellent wafer CD, overlay and defect control are also required. In this paper, we discuss two wafer CD uniformity issues, the effect of the reticle black border and photon shot noise. The readiness of EUV lithography for N10 will be discussed by showing on-product imaging and overlay performance of a self aligned via layer inserted with EUV lithography. EUV single patterning results will be discussed by comparing the imaging performance of our NXE:3100 cluster to the NXE:3300 at ASML. Last but not least, the extendibility of EUV lithography towards sub 10nm patterning will be discussed by demonstrating sub 10nm half pitch LS patterns with EUV single Self Aligned Double Patterning (SADP).
Extreme ultraviolet (EUV) lithography is currently the most promising technology for advanced manufacturing nodes. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool using the latest Interuniversity Microelectronics Center baseline resist Shin-Etsu SEVR59. In total ~1300 critical dimension (CD) measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32 nm. Both one-dimensional and two-dimensional structures through CD and pitch were measured. The reticle used in this calibration exercise allowed one to modulate flare by varying tiling densities. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different types through pitch and CD were used to calibrate the shadowing correction. The model calibration yielded an root-mean square of ~1 nm, which was observed to improve by including reticle CD data. An EUV mask fully corrected for optical proximity correction, flare and shadowing was fabricated and qualified, demonstrating the effectiveness of the implemented corrections.
Extreme Ultraviolet Lithography (EUVL) is currently the most promising technology for advanced manufacturing nodes:
it recently demonstrated the feasibility of 32nm and 22nm node devices, and pre-production tools are expected to be
delivered by 2010. Generally speaking, EUVL is less in need of Optical Proximity Correction (OPC) as compared to
193nm lithography, and the device feasibility studies were indeed carried out with limited or no correction. However, a
rigorous optical correction strategy and an appropriate Electronic Design Automation (EDA) infrastructure is critical to
face the challenges of the 22nm node and beyond, and EUV-specific effects such as flare and shadowing have to be fully
integrated in the correction flow and properly tested. This study aims to assess in detail the quality of a full chip optical
correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects.
Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool (ADT) using the latest IMEC baseline
resist Shin-Etsu SEVR59. In total about 1300 CD measurements at wafer level and 700 at mask level were used as input
for model calibration and validation. The smallest feature size in the data set was 32nm. Both one-dimensional and two-dimensional
structures through CD and pitch were measured. The mask used in this calibration exercise allowed the
authors to modulate flare by varying tiling densities within the range expected in the final design. The OPC model was
fitted and validated against the CD data collected on the EUV ADT. The shadowing effect was modeled by means of a
single bias correction throughout the design. Horizontal and vertical features of different type through pitch and CD were
used to calibrate the shadowing correction, and the extent of the validity of the single bias approach is discussed. In
addition, the quality of the generated full-chip flare maps has been tested against experimental results, and the model has
been validated in the full flare range available within the mask. The model calibration yielded an RMS of about 1nm, and
a EUV mask fully corrected for OPC, flare and shadowing was finally fabricated and qualified.
One of the main experimental setups for EUV lithography is the ASML EUV Alpha-Demo Tool (ADT), which achieves the first full-field EUV exposures at a wavelength of 13.6nm and a numerical aperture of 0.25. We report on the assessment of the baseline imaging performance of the ADT installed at IMEC, and review the work done in relation to EUV reticles and resists. For the basic imaging performance of the ADT, we have studied 40 LS patterns through dose and focus and at multiple slit positions, to extract exposure latitude and depth of focus. Measurements of reticle CD vs. wafer CD were done to determine the Mask Error Enhancement Factor (MEEF) for dense features. We also discuss the uniformity of the different features across the field, and the factors that influence it. The progress in EUV resist performance has been tracked by screening new materials on the EUV ADT. Promising resist materials have been tested on the ASML ADT and have demonstrated sub 32nm Line/Space and 34nm dense contact hole resolution. One of the main topics related to EUV reticles is reticle defectivity along with reticle defect printability. We have experimentally measured the number of wafer defects that repeat from die-to-die after reticle exposure on the ADT. To examine the wafer signature of the repeating defects, a SEM-based defect review is then conducted. We have used rigorous simulations to show that the defect signature on wafer can correspond to a relatively large ML defect, which can print as a hollow feature.
A research program on EUV lithography has been started at IMEC, based on ASMLs EUV full field scanner, the Alpha
Demo Tool (ADT). It contains three main projects: EUV resists, EUV reticles and assessment of the ADT performance.
The intent of this program is to help improve and establish the necessary mask and resist infrastructure, and achieve
learning to prepare for the use of EUV lithography in future production of integrated circuits. Good progress in resist
performance, as assessed by interference lithography, is illustrated by the ability of some materials to resolve 25nm HP.
In its initial phase, the reticle project has concentrated on working with the mask and blank suppliers to assure timely
availability of reticles for the ADT. An overview is given of the other reticle related activities, as well as first results of
a defect printability assessment by simulation and a study of blank reflectivity control. Guidance is given to the EUV
mask infrastructure to assure timely availability of reticles, first for the alpha demo tool (ADT), but also in preparation
for future use of EUV lithography in production. In the ADT assessment project, simulation studies are reported aimed at
the development of optical correction for flare and reticle shadowing effects. The impact of flare and shadowing effects
are well understood Strategies for flare mitigation and shadowing effect correction are proposed.
IMEC has started an EUV lithography research program based on ASMLs EUV full field scanner, the Alpha Demo Tool
(ADT). Currently, the ADT is in the final phase of installation. The program focuses on three main projects: EUV
resists, EUV reticles and assessment of the ADT performance. The intent of this program is to help improve and
establish the necessary mask and resist infrastructure. In this paper, the status and the progress of the program is
reviewed. In preparation for a resist process for the ADT, interference lithography has been used to track the progress of
resist performance. Steady progress in resist development is seen, especially in terms of resolution, as some materials
are now able to resolve 25nm HP. In its initial phase, the reticle project has concentrated on working with the mask and
blank suppliers to assure timely availability of reticles for the ADT. An overview is given of the other reticle related
activities, as well as first results of a defect printability study by simulation. In the ADT assessment project, simulation
studies are reported aimed at the development of optical correction for flare and reticle shadowing effects. The impact of
flare and shadowing effects are well understood and strategies for flare mitigation and shadowing effect correction are
proposed.
Lithographers are preparing their processes for the 130nm node. About one year ago, first generation full field ArF step and scan systems have been introduced in a number of fabs. These systems have lenses with numerical apertures in the order of 0.6. At the same time, 0.7 NA KrF step and scan systems have been introduced as well. Also last year, KrF resists were shown to be much more mature than ArF resists.
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