Excursion prevention is one of the key points in the mission of leading edge foundries. In this paper, we concentrate on patterning excursions and how to prevent them. This strategy concentrates pro-actively on the task to minimize the distributions of critical input parameters as much as possible, independently upon a certain pre-defined specification is met or not. In our paper, we will describe this concept by improving intra-field CDU using CD Correction (CDC) by mask tuning. Mask Tuning by the ForTune system uses ultra-short pulse laser technology to locally change the mask transmission, based on the wafer intra-field CDU, and hence improves CDU on wafer (CDC). To ensure a save patterning with a large enough process window without any negative yield or reliability impact, our concept looks for the tail of the final CD distribution instead of traditional 3-sigma numbers. By using a calibrated 3D resist model, we simulate the wafer CD distribution under all combinations of the Litho input parameter distributions dose, focus and mask CDU. As a result of the simulation, we get thousands of CD-results. The tail of that CD distribution still needs to be larger than the minimum CD needed for a safe etch transfer. Based on our simulation data we can calculate patterning failure probabilities and thus expected yield loss for the different patterning cases, including systematic process deviations (mask, dose, focus). At the final step, we will show in detail how the pro-active optimization of intra-field CDU by Mask Tuning using the ForTune CDC process will give us more patterning margin and thus will reduce the failure probability dramatically. The calculated yield loss for the worst scenario (focus and dose offset additionally to the mask signature) will be reduced from several percentages close to zero.
Within the current paper, we will concentrate on the well-known CDC technique from Carl Zeiss to improve the CD distribution of the wafer by improving the reticle CDU and its impact on hotspots and Litho process window. The CDC technique uses an ultra-short pulse laser technology, which generates a micro-level Shade-In-Element (also known as "Pixels") into the mask quartz bulk material. These scatter centers are able to selectively attenuate certain areas of the reticle in higher resolution compared to other methods and thus improve the CD uniformity.
In a first section, we compare the CDC technique with scanner dose correction schemes. It becomes obvious, that the CDC technique has unique advantages with respect to spatial resolution and intra-field flexibility over scanner correction schemes, however, due to the scanner flexibility across wafer both methods are rather complementary than competing. In a second section we show that a reference feature based correction scheme can be used to improve the CDU of a full chip with multiple different features that have different MEEF and dose sensitivities. In detail we will discuss the impact of forward scattering light originated by the CDC pixels on the illumination source and the related proximity signature. We will show that the impact on proximity is small compared to the CDU benefit of the CDC technique.
Finally we show to which extend the reduced variability across reticle will result in a better common electrical process window of a whole chip design on the whole reticle field on wafer. Finally we will discuss electrical verification results between masks with purposely made bad CDU that got repaired by the CDC technique versus inherently good “golden” masks on a complex logic device. No yield difference is observed between the repaired bad masks and the masks with good CDU.
OPC Verification is important to identify the critical wafer hotspots prior to mask fabrication. It helps to identify process limiting structures and possible yield limiters. These hotspots are also used by litho engineers to set up process conditions upfront. OPC Verification generally involves verification done at nominal and process window conditions. The process window conditions take into consideration typical process variations for lithography. In this standard flow, the post CMP topography variation was also lumped into these process variations via focus. But in current technologies especially in higher metal layers, CMP induced topography variation has become a major contributor to limit the overall process window. This results in different best focus for structures with different topography. This gives rises to requirement of OPC Verification flow taking into account these location-specific variations in order to know if the mask data can be used or not. This paper proposes a method to incorporate the topography induced focus shift into the OPC Verification flow. OPC Verification checks are performed at the new nominal and Process window conditions to identify the real hotspots seen on wafer. Results are shown where the highlighted hotspots with the proposed new flow correlate better with wafer results. Runtime was also taken into consideration when the flow was developed. Experiments on various products show better accuracy with minimal runtime impact.
CMP effects on manufacturability are becoming more prominent as we move towards advanced process nodes, 28nm and below. It is well known that dishing and erosion occur during CMP process, and they strongly depend on pattern density, line spacing and line width [1]. Excessive thickness or topography variations can lead to shrinkage of process windows, causing potential yield problems such as resist lifting or printability issues. When critical patterns fall into regions with extreme topography variations, they would be more sensitive to defects and could potentially become yield limiters or killers. Scanner tools compensate and correct topography variations by following the given profile [2]. However the scanner exposure window size is wider compared to local topography variations in design. This difference would generate new lithography focus sensitive weak points which may be missed. Experiments have been conducted as shown in Fig 1. Design under manufacturing has been subjected to scanner tool topography focus corrections. Despite of the corrections, Site B topography height has worsened while site A and C shown some improvements. As a result, additional improvements need to be done to meet manufacturability requirements.
KEYWORDS: Optical proximity correction, 3D modeling, Calibration, Scanning electron microscopy, Data modeling, Performance modeling, 3D metrology, Cadmium, Lithography, Image quality
OPC model of high quality relies on the accumulation of thousands of CD-SEM measurements with the drawback of long cycle time for data collection. Moreover regular CD measurements are not robust when dealing with critical bi-dimensional structures. In this paper, we propose to use SEM image contours for OPC model calibration and demonstrate the advantage in term of metrology work load. Two set of contours based on resist top and resist bottom measurements are extracted after lithography to generate simultaneously two OPC models. The performances of both models are evaluated with respect to rigorous S-Litho simulations. The model based on the resist bottom is very well matched with the rigorous simulation whereas the model based on resist top is not always following the rigorous simulation. It appears that resist thickness variations on specific hotspots is not compatible with the assumption of a simulated contour located in a single plane in resist.
KEYWORDS: 3D modeling, Photomasks, Chemical mechanical planarization, Semiconducting wafers, Lithography, Calibration, Finite element methods, 3D metrology, Computer simulations, Reticles
Process margin is getting critical in the present node shrinkage scenario due to the physical limits
reached (Rayleigh’s criterion) using ArF lithography tools. K1 is used to its best for better resolution and
to enhance the process margin (28nm metal patterning k1=0.31). In this paper, we would like to give an
overview of various contributors in the advanced technology nodes which limit the process margins and
how the challenges have been tackled in a modern foundry model.
Advanced OPC algorithms are used to make the design content at the mask optimum for patterning.
However, as we work at the physical limit, critical features (Hot-spots) are very susceptible to litho
process variations. Furthermore, etch can have a significant impact as well. Pattern that still looks
healthy at litho can fail due to etch interactions. This makes the traditional 2D contour output from ORC
tools not able to predict accurately all defects and hence not able to fully correct it in the early mask
tapeout phase. The above makes a huge difference in the fast ramp-up and high yield in a competitive
foundry market. We will explain in this paper how the early introduction of 3D resist model based
simulation of resist profiles (resist top-loss, bottom bridging, top-rounding, etc.,) helped in our
prediction and correction of hot-spots in the early 28nm process development phase. The paper also
discusses about the other overall process window reduction contributors due to mask 3D effects, wafer
topography (focus shifts/variations) and how this has been addressed with different simulation efforts in
a fast and timely manner.
KEYWORDS: 3D modeling, Calibration, Photoresist processing, Data modeling, Scanning electron microscopy, 3D metrology, Etching, Process modeling, Atomic force microscopy, Lithography
3D Resist Models are gaining significant interest for advanced technology node development. Correct prediction of resist profiles, resist top-loss and top-rounding are acquiring higher importance in ORC hotspot verification due to impact on etch resistance and post etch results. We would like to highlight the specific calibration procedure to calibrate a rigorous 3D model. Special focus is on the importance of high quality metrology data for both a successful calibration and for allowing a reduction of the number of data points used for calibration [1]. In a productive application the calibration could be performed using a subset of 20 features measured through dose and focus and model validation was done with 500 features through dose and focus. This data reduction minimized the actual calibration effort of the 3D resist model and enabled calibration run times of less than one hour. The successful validation with the complete data set showed that the data reduction did not cause over- fitting of the model. The model is applied and verified at hotspots showing defects such as bottom bridging or top loss that would not be visible in a 2D resist model. The model performance is also evaluated with a conventional CD error metric where CD at Bottom of simulation and measurement are compared. We could achieve excellent results for both metrics using SEM CD, SEM images, AFM measurements and wafer cross sections. Additional modeling criterion is resist model portability. A prerequisite is the separability of resist model and optical model, i.e. the resist model shall characterize the resist only and should not lump characteristics from the optical model. This is a requirement to port the resist model to different optical setups such as another illumination source without the need of re-calibration. Resist model portability is shown by validation and application of the model to a second process with significantly different optical settings. The resist model can predict hot spots and CDs for the second litho process with the same quality as for the process it was calibrated to.
The Fraunhofer Institute for Photonic Microsystems (IPMS) develops and fabricates MOEMS micro-mirror arrays for a
variety of applications in image generation, wave-front correction and pulse shaping. In an effort to extent the
application range, mirrors are being developed that withstand higher light intensities.
The absorbed light generates heat. Being suspended on thin hinges, and isolated from the bulk by an air gap, the mirrors
heat up. Their temperature can be significantly higher than that of their substrate.
In this paper we describe an experiment carried out to verify simulations on the temperature within the mirror plates
during irradiation. We created a structure out of electrically connected mirror plates forming a four-point electrical
resistor, and calibrated the thermal coefficient of the resistor in a temperature chamber. We irradiated the resistor and
calculated the mirror temperature.
In the experiment, the temperature in the mirror plates increased by up to 180 °C. The mirrors did not show significant
damage despite the high temperatures. Also, the experiment confirms the choice of heat transport mechanisms used in
the simulations. The experiment was done on 48 μm x 48 μm mirrors suspended over a 5 μm air gap, using a 355 nm
solid-state laser (4 W, up to 500 W/cm2).
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