The paper presents the results of a study to define a production-worthy inspection technique for subresolution solid and hollow scattering features used in 193-nm lithography. Masks are inspected using conventional high-NA and aerial-imaging-based mask inspection tools. Inspection results are compared regarding capture rate and nuisance defect rate.
The industry roadmap for IC manufacturing at design rules of 90nm and below foresees low k1-factor optical lithography at 193nm exposure wavelength. Aggressive model-based OPC are being used more and more frequently in order to achieve the extremely tight mask CD specifications required by 90nm technology node. State-of-the-art mask inspection is challenged to detect CD defects close to metrology resolution. Inspection of OPC is critical; OPC feature dimensions are usually near or below the resolution limits of mask exposure. In addition, chrome defects can be semitransparent and change the intensity of light on the wafer. In this paper aerial-image based mask inspection is investigated and presented. The concept inspects a given mask based on its aerial image with selected wafer exposure conditions, thus “finds only defect which will print”. This paradigm shift in mask inspection philosophy provides the unique opportunities of verifying and controlling the entire aerial image generated by the inspected mask. As reticle enhancement techniques like OPC are designed to enhance the aerial image of a mask, this concept offers a comprehensive way of inspecting these techniques. The inspection is shifted from detecting every single minor change on mask to detecting what on mask could possibly impact the printing image quality on the wafer. In this paper an advanced application of aerial-image based mask inspection is discussed in more detail. As a standard, the Aera193 uses the best-focus aerial image for defect detection. From HNA mask inspection it is a well-known fact, that shifting the inspection off-focus, can provide a more sensitive detection. In the csase of aerial-image based inspection, going off-focus can be compared with lithography exposure out of focus. In other words, the lithography process window will be taken into account for defect detection. This methodology provides additional important information
·Understand process window printability of defects detected at best-focus
·Detect additional defects, which may print at the borders of the process window.
This information is of extreme value for wafer lithography and may help by decisions about lithography process and mask usage.
Focus of the paper is to analyze the application of aerial image-based off-focus inspection. Advanced OPC test plates are used to analyze detection at best and off-focus. The inspection results are compared to actual wafer results. Wafer lithography benefit is discussed.
The inspection of alternating phase shifting masks is still one of the major challenges in state-of-the-art mask making. Main issue is that phase defects cannot easily be identified by inspection systems using an inspection wavelength different form the target exposure wavelength. The paper presents inspection results using the Aera193, an aerial image based mask inspection system.
Inspection of aggressive OPC represents one of the major challenges for today's mask inspection methodologies. Systems are phased with high-density layouts, containing OPC features far below the resolution limit of conventional inspection systems. This causes large amounts of false and nuisance defects, especially on production applications. The paper presents the use of Aera193, a new inspection system using aerial imaging as inspection methodology.
The industry roadmap for IC manufacturing at design rules of 90nm and below foresees low k1-factor optical lithography at 193nm exposure wavelength. The mask error enhancement factor (MEEF) describes the phenomenon in which errors in the mask critical dimensions (CDs) are not transferred to the wafer in direct proportion to the optical reduction value of the lithography system. In the low-k1 area, the MEEF becomes a significant problem, as it consumes a larger than anticipated percentage of the CD tolerance budget. As a result mask CD uniformity requirements have been tightened significantly to find MEEF-related CD defects prior to the first printing at the wafer fab. The challenge for today's mask inspection methodology lays in the way defects are detected. Conventional mask inspection detects defects according to their dimensions on the mask. Finding MEEF-related CD defects is a challenge as these defects are often caused by CD deviations close to metrology resolution. The paper investigates CD uniformity control using aerial image based mask inspection. The fundamental difference to today's inspection methodology is that a defect is detected based on its impact onto the aerial image projected by the given mask. In order to emulate the aerial image, lithography condition like Numerical Aperture and illumination need to be known to the inspection system. As a large portion of the MEEF is based on the lithography exposure system, MEEF defects can be detected.
The industry roadmap for IC manufacturing at design rules of 90nm and below foresees low k1-factor optical lithography at 193nm exposure wavelength. Aggressive model-based OPC and Phase Shift Mask technology are being used more and more frequently in order to achieve the extremely tight mask CD specifications required by 90nm technology node. State-of-the-art mask inspection is challenged to detect CD defects close to metrology resolution. Inspection of OPC and PSM masks is critical; OPC feature dimensions are usually near or below the resolution limits of mask exposure. In addition, chrome defects can be semitransparent and change the intensity of light on the wafer. In this paper aerial-image based mask inspection is investigated and presented. The concept inspects a given mask based on its aerial image with selected wafer exposure conditions, thus 'finds only defect which will print'. This paradigm shift in mask inspection philosophy provides the unique opportunities of verifying and controlling the entire aerial image generated by the inspected mask. As reticle enhancement techniques like OPC and EAPSM are designed to enhance the aerial image of a mask, this concept offers a comprehensive way of inspecting these techniques. The focus of the inspection is shifted from detecting every single minor change on mask to detecting what on mask could possibly impact the printing image quality on the wafer. The focus of the paper is to analyze the impact of different exposure and lithography process conditions onto the inspection sensitivity. The standard defect sensitivity and runability test mask UIS10 and other advanced real production masks were printed under different exposure and process conditions resembling production-worthy 193nm lithography processes. The masks then were inspected using Etec's aerial image-based inspection concept. Detection sensitivities and CD variations on the wafer are analyzed and compared.
The paper presents a new technology to inspect alternating phase shifting masks. Instead of finding defects based on a size-dependent defect specification, defects are found according to their impact at the wafer CD result. The inspection methodology used is aerial imaging. Phase effects are taking into account inherently. The main advantage of this method is that only defects, which actually affect the wafer result, will be detected and classified. The paper presents first inspection results on alternating phase shifting test masks designed for the 70nm generation.
The paper presents a revolutionary technology to inspect advanced contact layers. Instead of finding defects based on a size-dependent defect specification, defects are found according to their impact at the wafer CD result. The inspection methodology used is aerial imaging. The main advantage of this method is that only defects, which actually affect the wafer result, will be detected and classified. The paper presents first inspection results on contact layers designed for the 130nm and 90 nm technology node.
The paper presents a new technology to inspect alternating phase shifting masks. Instead of finding defects based on a size-dependent defect specification, defects are found according to their impact at the wafer CD result. The inspection methodology used is aerial imaging. Phase effects are taking into account inherently. The main advantage of this method is that only defects, which actually affect the wafer result, will be detected and classified. The paper presents first inspection results on alternating phase shifting test masks designed for the 70nm generation.
The paper presents results of a thorough study using the UV- based die-to-database mask inspection system ARIS100i for the inspection of alternating phase shifting masks (AAPSM) designed for KrF (248nm) technology. A specifically designed test mask was used to investigate sensitivity limitations of the i-line tool. Main focus is on phase errors, which were treated as a function of defect size, phase, and mask location.
The paper presents the use of the Linewidth Bias Monitor (LBM), the critical dimension (CD) uniformity mapping option of the ARIS 2li die-to-database mask inspection system, for incoming quality control (IQC) in the wafer fab. LBM is qualified for this purposes by comparing it's quantitative results with CD measurements. Masks, provided by different commercial vendors, are evaluated based on the LBM maps obtained during mask inspection. Mean-to-target and 3-sigma values are evaluated and compared.
Embedded attenuated phase shift masks (EAPSMs) are being used in the semiconductor industry for high-density patterning of critical layers, such as gate and contact layers of circuit devices, of the 130 nm node and beyond. This paper focuses on the manufacturing and inspection of ternary (tritone) phase shift masks designed for the 130 nm design-rule generation. The manufacturing flow is presented and the use of the ARISTM100i mask inspection system for inspection is demonstrated.
The paper presents the inspection of embedded attenuated phase shift masks for the 193nm lithography generation using UV-based mask inspection systems. Production issues like light calibration due to the existence of different transmissions on the mask and halftone-specific inspection sensitivity settings are discussed. A mask inspection example is presented and the most severe defect types are analyzed. In addition, the mask is investigated using the Linewidth Bias Monitor (LBM) option of the inspection system used, which provides a critical dimension (CD) uniformity map of the entire mask.
The paper presents results of a thorough study using the UV-based die-to-database mask inspection system ARISTM100i for the inspection of alternating phase shifting masks (AAPSM) designed for ArF (193nm) technology. Specially designed test masks were used to investigate sensitivity limitations of the i-line tool. Main focus is on phase errors, which were treated as a function of defect size, phase, and mask location. In addition, production reticles were inspected using a specially developed sensitivity AAPSM. Production issues like false defect rate and data preparation were addressed. The paper is concluded with a short printability analysis of different phase defects detected during the experiment.
The paper presents the use of the Linewidth Bias Monitor (LBM), the critical dimension (CD) uniformity mapping option of the ArisTM21i die-to-database mask inspection system, for mask process control and incoming quality control (IQC) in the wafer fab. LBM is qualified for this purposes by baselining it with CD measurements. Masks, provided by different commercial vendors, are evaluated based on the LBM maps obtained during mask inspection. Mean-to-target and 3-sigma values are evaluated and compared. The results are presented. In addition, a case, where LBM identified a killer CD variation during IQC is presented.
With the advent of system-on-chip (SOC) devices, resolving typical problems of composite designs is getting more urgent. The continuous effort for achieving tighter critical dimension (CD) tolerances together with the known phenomena of pattern density loading makes the mask fidelity issue for SOC technology a unique and prominent issue. The typical characteristic of an SOC with respect to CD control is the diversity of linewidths and pattern density over the chip. This paper presents the metrology software called Linewidth Bias Monitor (LBM) as a method to characterize pattern-loading effects on an SOC.
Recently a new mask qualification concept is getting more and more attention. Mask makers are challenged to meet mask and defect specifications of 130 and 100-nm technology node. This means very tight specifications, which usually lead to long mask delivery times. A main factor in the mask making process is mask inspection and repair. The mask repair cycle is not only time-consuming, but also bears the danger of damaging a mask. At the same time, when investigating defect printability, it is getting clear that a lot of today detected defects do not affect wafer-printing results at all. The concept Inspect all - Repair only what prints is introduced. In this paper a study comparing different defect classification methods and their impact on mask repair cycle time is presented.
This paper examines the effects of mask printability of various OPC defect types on a MoSi APSM mask using an MSM-100 AIMS tool operating at 248nm as a printability prediction tool. Printability analysis will be used to address differences in intensity, image capture wavelength, defocus, defect size, type, and placement on two substrate materials. Defect correlation to photomask CD error, aerial image intensity error, and MEEF on high-end KrF photomasks will also be studied.
CD uniformity is one of the key discussion topics in the ramp-up process of new technologies. The impact of mask quality is getting more and more attention in this process. The paper presents improving wafer CD uniformity control by application of new reticle CD qualification procedure. The new procedure is based on combining conventional CD metrology and Linewidth Bias Monitor (LBM) as a standard part of mask inspection.
While the semiconductor industry is following a very aggressive roadmap without a corresponding reduction in exposure wavelength, the role of resolution enhancement techniques like PSM and OPC is becoming more and more important. Mask making for these advanced techniques is one of the most crucial parts in making these techniques work. Mask inspection is one of the major challenges in the mask making process, as it is one of the most performance critical steps in the entire mask making process. Especially contact or OPC patterns show difficulties in die-to-database inspection as the CAD data asks for square corners. LPC is a mask enhancement technique improving image quality and CD linearity for laser pattern generators. The paper present the impact of Laser Proximity Correction on contact and line patterns of 0.18 micrometers generation. The LBM is used to characterize Cd uniformity improvement of the entire plate.
Inspection is one of the major challenges in mask making, as it is one of its most performance crucial steps in the entire mask making process. Especially contact patterns show difficulties in die-to-database inspection as the CAD data asks for square corners. The paper presents the impact of Laser Proximity Correction (LPC) on the inspectability of contact and line patterns. LPC is a mask enhancement technique improving image quality and CD linearity for laser pattern generators. The use of the linewidth bias monitor tool in order to characterize CD uniformity over the entire plate is demonstrated.
The incorporation of laser proximity correction into mask production is presented. The ALTA 3000 has been chosen for demonstration. The goal is to improve pattern fidelity of the ALTA 3000 to a level comparable to the ALTA 3500. This provides the possibility to shift production from the ALTA 3500 to the ALTA 3000 and extends the lifetime of an ALTA 3000. The paper focuses on demonstrating different applications and the incorporation into the standard mask production flow.
Optical proximity correction is one of the major hurdles chip manufacturing has to overcome. The paper presents evaluation results of CAPROX OPC, a rule based OPC software. Mask making influences as well as production requirements are discussed. Rule generation, one of the most critical parts in a rule based correction scheme is discussed. Two different applications are presented.
A hierarchical rule based optical proximity effect correction approach is presented. The approach has been driven by maskmaking and production requirements to make OPC a practical problem solution. The model based rule generation is presented, as well as benchmark tests on different state-of- the-art test chips.
The application of Optical Proximity Correction for improving uniformity of printed dimensions at sub-half-micron resolution in a 0.35 micron CMOS process is described. Results are presented in terms of measurements made on polysilicon gates, at different pitches, which are compared to the uncorrected case. The impact of photomask and stepper lens qualities on dimensional control are also considered. Results presented are at the demonstrator stage but strategy for implementation in production is discussed.
With smaller feature sizes and higher pattern densities on high end reticles for DUV lithography, pattern fidelity on mask features becomes essential for wafer lithography performance. The corner rounding on the mask directly results in line shortening on the wafer. One of the main disadvantages of modern laser pattern generating tools for mask making like the ALTA tools, compared to electron beam tools like the latest MEBES4500, is pattern fidelity. The corner radius on photo-masks is mainly determined by the beam spot diameter used for printing, and the resist and chrome etching process following. This paper will discuss the possibility to reduce corner rounding on ALTA reticles by applying small serifs to feature corners in the ALTA exposure data by automatic software correction of the original design data. Issues as correction time of a chip, increase in data volume and the effect on mask manufacturing will be discussed. High resolution images, CD-measurements and aerial images of regular and corner rounding improved features will be compared. The gain in corner rounding of masks manufactured on the ALTA3000 and ALTA3500 are evaluated. Feasibility and applicability of that method in a mask shop manufacturing flow is discussed.
KEYWORDS: Monte Carlo methods, Silicon, Gold, Electron beam lithography, Optical simulations, Scattering, Chemically amplified resists, Polymethylmethacrylate, Electron beams, Diffusion
A fast simulator for electron beam lithography called SELID, is presented. For the exposure part, an analytical solution based on the Boltzmann transport equation is used instead of Monte Carlo. This method has been proved much faster than Monte Carlo. All important phenomena are included in the calculation. Additionally, the reaction/diffusion effects occurring during post exposure bake in the case of chemically amplified resists are taken into account. The result obtained by the simulation are compared successfully with experimental and other simulation results for conventional and chemically amplified resists. The case of substrates consisting of more than one layer is considered in depth as being of great importance in electron beam patterning. By using SELID, it is possible to forecast the resist profile with considerable accuracy for a wide range of resists, substrates and energies. Additionally, proximity effect parameters are extracted easily for use in any proximity correction package.
KEYWORDS: Mask making, Raster graphics, Photomasks, Critical dimension metrology, Data corrections, Scattering, Electron beam lithography, Sun, Control systems, Data conversion
The e-beam proximity effect is well known as one of the limiting factors in e-beam lithography. As features get smaller the need for e-beam proximity effect correction increases. There exist different approaches to cover these effects by varying dose or shape of the pattern layout during the exposure step. Whichever algorithm is used, the question of proximity effect correction gets more and more a performance problem for forefront applications like the 256 megabit and 1 gigabit chips. The correction approach has to handle large data volume in reasonable time. Key to overcome this hurdle is to include hierarchial data handling into the proximity correction algorithm, which involves hierarchical data structures as well as hierarchy reorganization methods. The goal of the present work is to perform all necessary steps in order to guarantee the accuracy of the exposure result for the 1 gigabit memory chip. One step of the preparation is the e-beam proximity correction for raster scan machines. With respect to proximity effect correction, raster scan machines have a severe drawback. The scanning speed is constant while writing the layout, i.e., dose variation is not applicable to compensate for the proximity effect. There is, however, the geometry which can be exploited as degree of freedom. Geometrical variations of the layout underlie many constraints such as neighboring features, the exposure grid of the e-beam tool and, but not least, writing time. The paper presents how to solve some of the major problems occurring when proximity effect correction becomes an unavoidable step in the mask making process. Power and application limits of proximity effect correction for raster scan machines are investigated. The exposure has been carried out on a MEBES 4500 system. Process latitude and line width linearity are presented. In addition, practical questions like file size increase due to proximity correction are investigated. Exposure results of uncorrected and corrected pattern are compared to demonstrate the necessity of the correction as well as the improvement in pattern fidelity.
KEYWORDS: Monte Carlo methods, Electron beam lithography, 3D displays, Backscatter, Optical simulations, Diffusion, Lithography, Electron beams, Scattering, Laser scattering
In the e-beam world a simulator, comparable to well established optical simulators, has not been available so far. SELID (Simulation of E-Beam Lithography in 3 Dimensions) closes this gap by providing a comprehensive simulation tool covering most aspects of today's advanced e- beam lithography, such as process optimization and parameter determination for the e-beam proximity effect correction. SELID consists of 4 major parts: the simulation of the exposure step, the post-exposure bake and the resist development, and the analysis part. On output it displays many different views into the exposed image, 2D exposure images, as well as 2D resist profiles and resist structures in full 3D rendering. This paper presents first results using SELID. The application to direct write will be demonstrated. A commercially available positive e-beam resist was used for electron beam direct write lithography applications. Process optimization and the accuracy of the simulator will be demonstrated. Moreover, the agreement between experiment and simulation will be investigated.
Both e-beam and optical proximity effects are still a major barrier in the transfer of an ULSI design from the CAD station to the printed result on wafer. Optical proximity effect correction (OPC) is shown to be a strong tool to improve the printing latitudes for i-line lithography of 0.35 micrometers feature sizes and below, but leads to fractal geometries around 0.1 micrometers (corresponding to 0.5 micrometers on a 5x reticle). This quantum leap in required minimum linewidth on the mask may urge mask makers to apply e-beam proximity effect correction (PEC), even more than a decrease in the reticle magnification from 5x to 4x (and further) would. For raster scan e-beams, which are typically used in mask making, correction by dose variation is not practical. Hence, PEC for these systems must be tackled by modifying the geometry of the design, in a way similar to OPC techniques. Both corrections must compromise between the accuracy achieved, which is dominated by the selected (correction and exposure) grid size, and the resulting throughput loss, caused by the use of a smaller grid size. Sigma-C now introduces a new algorithm, which enables the proximity effect correction by shape variation. It is included into CAPROX and supports hierarchy in the same manner as the other postprocessing operations. The exposure of the shape corrected pattern on a raster scan machine requires only one beam pass, whereas dose variation would require one pass for each dose. Exposures were made at IMEC and at Compugraphics. The first results on Leica EBMF10.5 and MEBES III are promising. The pure shape correction increases the line width uniformity and opens the process window for critical dimensions below 1 micrometers . Performance measurements show that the 64 Mb DRAM is a job of a few hours.
The proximity effect in e-beam lithography is well known and many solutions exist to correct it. But none of them are able to cope with the amount of data in today's large scale memories. In a conventional approach, the 64 Mb DRAM would lead to 10 Gigabytes of flat data and weeks of processing time, for example. Recently, Sigma-C achieved a breakthrough in handling USLIs by developing a generic algorithm for many different hierarchical processes. It solves throughput problems for operations like overlap removal (OLR); the e-beam (EPC) and optical proximity correction (OPC) which, at first glance, are inaccessible to hierarchical processing. Hierarchical algorithms take advantage of the growing symmetry of a layout with the number of designed shapes. Even after all processing steps a ULSI device will have hierarchy, not necessarily the same as on input, but yet enough to significantly decrease processing times. Hierarchical processing is a general outline which can be used for many different applications. Most parts of this algorithmic scheme are identical, only one part must be adapted for each application. This paper shows the general outline of hierarchical processing and the solution of the algorithmic steps specific to the hierarchical e-beam proximity correction. Subsequently, the application on a variety of critical layers of the 64 and 256 Mb DRAM is demonstrated using a workstation. Corrected and uncorrected exposures are compared by SEM pictures and line width measurements. The correction not only opens the process window, it turns out to be an enabling technique for critical layers.
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