The development of an assembly and packaging process for MEMS deformable mirrors (DMs) with
through wafer via (TWV) interconnects is presented. The approach consists of attaching a DM die with
high-density TWV electrostatic actuator interconnects to an interposer substrate that fans out these
connections for interfacing to conventional packaging technology.
Improvements for open-loop control of MEMS deformable mirror for large-amplitude
wavefront control are presented. The improvements presented here relate to measurement
filtering, characterization methods, and controlling the true, non-differential shape of the
mirror. These improvements have led to increased accuracy over a wider variety of
deflection profiles including flattening the mirror and Zernike polynomials.
This letter reports the development of a novel microshunt by combining biocompatible materials with well-established, robust microelectromechanical systems (MEMS) fabrication processes. The key features of our microshunt fabrication process are summarized as follows: (1) Control over the thickness of channels' enclosure, (2) channels' height scalable by multiple thick resist patterning, (3) structural material deposition by electroplating, and (4) an easy fabrication process suitable for mass production. These features were realized using electroplating for the gold structural material, photoresist sacrificial material, and e-beam evaporation of adhesion layers. The combination of these techniques allows precise control on the microchannels width, depth, and length. A novel channel sealing technique that is extendable to more complex geometries is also presented. The developed method involves using a thin gold seed layer deposited via evaporation prior to electroplating the last structural layer, the cover of the channels. This method enhanced the electroplating process, yielding more control of the final thickness of the cover layer compared to methods consisting of overgrowing the channels until they seal.
A new method is introduced for predicting control voltages that will generate a prescribed
surface shape on a deformable mirror. The algorithm is based upon an analytical elastic
model of the mirror membrane and an empirical electromechanical model of its actuators. It
is computationally simple and inherently fast. Shapes at the limit of achievable mirror spatial
frequencies with up to 1.5μm amplitudes have been achieved with less than 15nm RMS error.
We report on the development of a new class of electrostatic MEMS deformable mirror (DM) fabricated through a
combination of bulk micromachining, wafer bonding, and surface micromachining. The combination of these
fabrication technologies introduces four major improvements over previous MEMS DMs, which are fabricated using
surface micromachining alone. First, the MEMS DM structural components (mirror surface and actuator array) are
made entirely of single crystalline silicon by use of the device layer of a whole 4-inch silicon-on-insulator (SOI)
wafer bonded together via anodic bonding. Unlike current MEMS DMs fabricated entirely using surface
micromachining, bulk micromachining steps in this fabrication process require no etch access holes, print through is
inexistent, and no polishing steps are required. This leads to reduced diffraction of light from the mirror surface,
improved mirror surface optical quality, and elimination of manufacturing processing steps. Second, through-wafer
interconnects are used to connect the densely-packed electrostatic actuator array to driver electronics. This
eliminates the need for wirebonding at the periphery of the DM, increasing the surface area available for actuators
and removes the need for bulky wire bundles to connect the device to its driver. Third, by using the full area of a
silicon wafer for each mirror, these MEMS DMs offer a larger optical aperture than any previously-reported MEMS
DM. The larger aperture will achieve higher angular resolution, providing larger wavefront correction. Finally, the
mirror and actuator thicknesses are not limited to several micrometers, unlike in surface micromachining. The
thickness limits using this fabrication process is prescribed by the device layer thickness in SOI wafers, which vary
between several micrometers to several hundred of microns.
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