The Design Rule Manual (DRM) is a critical component in the introduction and release of new technology nodes. It is the reference manual of definitive requirements, documented in detail, on all information regarding design rules and technology node design requirements. The DRM is a contract between the foundry and the designer. Designs must meet all documented requirements to be accepted for manufacture. The DRM’s critical role in process design enablement obligates it to a very high quality standard. The DRM must be accurate, reliable, and clear of ambiguity. Qualification of the DRM is crucial as design rules become extremely complex with advancing technology. DRM teams must ensure all descriptions and figures are correct and clear versus target requirements from the beginning of the technology development stage. The qualification process should cover all typical cases as well as corner and unexpected cases. Traditional methods of targeted pattern creation leave gaps in ensuring a high quality DRM. Those methods often miss complex scenarios leading to incomplete DRM documentation or descriptions with vague ambiguity. Ambiguity in the DRM leads to improper DRC rule coding, resulting in erroneous DRC checking. This paper presents a synthetic pattern/layout generation approach to high quality and high coverage DRM and DRC qualification. The generated patterns flow into a post-generation-analysis-fix step that helps discover and analyze issues while initial design rules and DRC code is being developed. Guided random generation of legal layout patterns produces simple and complex pattern configurations to challenge the accuracy and consistency between the original intention of the complex design rules and DRC rule deck. The post-generation-analysis-fix step helps identify locations of potential discrepancy. Flushing out these discrepancies and ambiguities drives enhancements to converge on robust DRM documentation and consistency between design rule intent and DRC run set implementation from early development throughout the life cycle of process node deployment.
KEYWORDS: Legal, Manufacturing, New and emerging technologies, Monte Carlo methods, Metals, Error analysis, Design for manufacturability, Design for manufacturing
Design rules are geometric constraints imposed on IC layout to ensure products can be manufactured at an acceptable yield. Designs are required to pass sign-off design rule check (DRC) before tape-out. Foundries rely on DRC to ensure designs they accept are manufacturable. DRC runsets must be accurate, complete, and reliable. DRC runset qualification is critical in technology node deployment and maturation. The number, complexity and variation of design rules grow dramatically with advancing technology nodes. This increases the QA challenge to ensure quality and accuracy of runsets and their interdependent rule operations. Traditional methods of migrating previous node QA patterns, manually crafting new testcases, and targeted-pattern generation leave gaps in advanced process node qualification coverage. We deploy a novel synthetic layout generation approach to produce large varieties of complex layouts with high design space coverage to thoroughly qualify runsets, make runset improvements and release quality PDKs. We employ guided random Monte Carlo layout generation with user-defined layout construction rules. User-defined rules inform DRC requirements and assign weighted priorities to guide layout design styles. We generate stress DR layouts and high pattern coverage, with DRC-clean patterns and with deliberate DRC violations, to validate expected DRC results and exercise entire rule decks. In this paper, we show how Synthetic Layout Generation is integrated into runset QA flows, automatically generating stress DR conditions that manual efforts often miss, expand layout pattern space coverage, and improve runset execution coverage leading to higher quality on-time PDK development, qualification, and release.
At the core of Design-technology co-optimization (DTCO) processes, is the Design Space Exploration (DSE), where different design schemes and patterns are systematically analyzed and design rules and processes are co-optimized for optimal yield and performance before real products are designed. Synthetic layout generation offers a solution. With rules-based synthetic layout generation, engineers design rules to generate realistic layout they will later see in real product designs. This paper shows two approaches to generating full coverage of the design space and providing contextual layout. One approach relies on Monte Carlo methods and the other depends on combining systematic and random methods to core patterns and their contextual layout. Also, in this paper we present a hierarchical classification system that catalogs layouts based on pattern commonality. The hierarchical classification is based on a novel algorithm of creating a genealogical tree of all the patterns in the design space.
As the litho hotspot detection runtime is currently in a continuous increase with sub-10nm technology nodes due to the increase of the design and process complexity, new methods and approaches are needed to improve the runtime while guaranteeing high accuracy rate. Machine-Learning Fast LFD (ML-FLFD) is a new flow that uses a specialized machine learning technique to provide fast and accurate litho hotspot detection. This methodology is based on having input data to train the machine learning model during the model preparation phase. Current ML-FLFD techniques depend on collecting hotspots (HS) and Non hotspots (NHS) data from the drawn layer in order to train the model. In this paper, we present a new technique where we use the retarget data to train the machine learning model instead of using the drawn hotspot data. Using retargeting data is getting one step closer to the actual printed contours which gives a better insight about the hotspots of the manufactured wires during the machine learning model training step. The effect of using closer data to the printed contours will be reflected on both the accuracy and the extra rate which will reduce simulation area. In the different sections of this paper, we will compare the new approach of using retarget data as a ML input to the current technique of using drawn data. Pros and cons of the two approaches will be listed in details including the experimental results of hotspot accuracy and litho simulation area.
As the typical litho hotspot detection runtime continue to increase with sub-10nm technology node due to increasing design and process complexity, many DFM techniques are exploring new methods that can expedite some of their advanced verification processes. The benefit of improved runtimes through simulation can be obtained by reducing the amount of data being sent to simulation. By inserting a pattern matching operation, a system can be designed such that it only simulates in the vicinity of topologies that somewhat resemble hotspots while ignoring all other data. Pattern Matching improved overall runtime significantly. However, pattern matching techniques require a library of accumulated known litho hotspots in allowed accuracy rate. In this paper, we present a fast and accurate litho hotspot detection methodology using specialized machine learning. We built a deep neural network with training from real hotspot candidates. Experimental results demonstrate Machine Learning’s ability to predict hotspots and achieve greater than 90% detection accuracy and coverage, with best achieved accuracy 99.9% while reducing overall runtime compared to full litho simulation.
KEYWORDS: Lithography, Visualization, Manufacturing, New and emerging technologies, Failure analysis, Multilayers, Logic, Reliability, Analytical research
As the IC technology node moves forward, critical dimension becomes smaller and smaller, which brings huge challenge to IC manufacturing. Lithography is one of the most important steps during the whole manufacturing process and litho hotspots become a big source of yield detractors. Thus tuning lithographic recipes to cover a big range of litho hotspots is very essential to yield enhancing. During early technology developing stage, foundries only have limited customer layout data for recipe tuning. So collecting enough patterns is significant for process optimization. After accumulating enough patterns, a general way to treat them is not precise and applicable. Instead, an approach to scoring these patterns could provide a priority and reference to address different patterns more effectively. For example, the weakest group of patterns could be applied the most limited specs to ensure process robustness. This paper presents a new method of creation of real design alike patterns of multiple layers based on design rules using Layout Schema Generator (LSG) utility and a pattern scoring flow using Litho-friendly Design (LFD) and Pattern Matching. Through LSG, plenty of new unknown patterns could be created for further exploration. Then, litho simulation through LFD and topological matches by using Pattern Matching is applied on the output patterns of LSG. Finally, lithographical severity, printability properties and topological distribution of every pattern are collected. After a statistical analysis of pattern data, every pattern is given a relative score representing the pattern’s yield detracting level. By sorting the output pattern score tables, weak patterns could be filtered out for further research and process tuning. This pattern generation and scoring flow is demonstrated on 28nm logic technology node. A weak pattern library is created and scored to help improve recipe coverage of litho hotspots and enhance the reliability of process.
As technology advances, the need for running lithographic (litho) checking for early detection of hotspots before tapeout has become essential. This process is important at all levels—from designing standard cells and small blocks to large intellectual property (IP) and full chip layouts. Litho simulation provides high accuracy for detecting printability issues due to problematic geometries, but it has the disadvantage of slow performance on large designs and blocks [1]. Foundries have found a good compromise solution for running litho simulation on full chips by filtering out potential candidate hotspot patterns using pattern matching (PM), and then performing simulation on the matched locations. The challenge has always been how to easily create a PM library of candidate patterns that provides both comprehensive coverage for litho problems and fast runtime performance. This paper presents a new strategy for generating candidate real design patterns through a random generation approach using a layout schema generator (LSG) utility. The output patterns from the LSG are simulated, and then classified by a scoring mechanism that categorizes patterns according to the severity of the hotspots, probability of their presence in the design, and the likelihood of the pattern causing a hotspot. The scoring output helps to filter out the yield problematic patterns that should be removed from any standard cell design, and also to define potential problematic patterns that must be simulated within a bigger context to decide whether or not they represent an actual hotspot. This flow is demonstrated on SMIC 14nm technology, creating a candidate hotspot pattern library that can be used in full chip simulation with very high coverage and robust performance.
In order to resolve the causality dilemma of which comes first, accurate design rules or real designs, this paper presents a flow for exploration of the layout design space to early identify problematic patterns that will negatively affect the yield.
A new random layout generating method called Layout Schema Generator (LSG) is reported in this paper, this method generates realistic design-like layouts without any design rule violation. Lithography simulation is then used on the generated layout to discover the potentially problematic patterns (hotspots). These hotspot patterns are further explored by randomly inducing feature and context variations to these identified hotspots through a flow called Hotspot variation Flow (HSV). Simulation is then performed on these expanded set of layout clips to further identify more problematic patterns.
These patterns are then classified into design forbidden patterns that should be included in the design rule checker and legal patterns that need better handling in the RET recipes and processes.
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