Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows real-time
virtual massive connectivity among huge number of neurons located on different chips.[1] By exploiting high
speed digital communication circuits (with nano-seconds timing), synaptic neural connections can be time multiplexed,
while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Neurons generate "events"
according to their activity levels. That is, more active neurons generate more events per unit time and access the interchip
communication channel more frequently than neurons with low activity. In Neuromorphic system development, AER
brings some advantages to develop real-time image processing system: (1) AER represents the information like time
continuous stream not like a frame; (2) AER sends the most important information first (although this depends on the
sender); (3) AER allows to process information as soon as it is received.
When AER is used in artificial vision field, each pixel is considered like a neuron, so pixel's intensity is represented like
a sequence of events; modifying the number and the frequency of these events, it is possible to make some image
filtering.
In this paper we present four image filters using AER: (a) Noise addition and suppression, (b) brightness modification,
(c) single moving object tracking and (d) geometrical transformations (rotation, translation, reduction and
magnification). For testing and debugging, we use USB-AER board developed by Robotic and Technology of Computers
Applied to Rehabilitation (RTCAR) research group. This board is based on an FPGA, devoted to manage the AER
functionality. This board also includes a micro-controlled for USB communication, 2 Mbytes RAM and 2 AER ports
(one for input and one for output).
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows a
real-time virtual massive connectivity between huge number neurons, located on different chips. By exploiting high
speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed,
while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate
"events" according to their activity levels. More active neurons generate more events per unit time, and access the
interchip communication channel more frequently, while neurons with low activity consume less communication
bandwidth. When building multi-chip muti-layered AER systems, it is absolutely necessary to have a computer interface
that allows (a) reading AER interchip traffic into the computer and visualizing it on the screen, and (b) converting
conventional frame-based video stream in the computer into AER and injecting it at some point of the AER structure.
This is necessary for test and debugging of complex AER systems. In the other hand, the use of a commercial personal
computer implies to depend on software tools and operating systems that can make the system slower and un-robust.
This paper addresses the problem of communicating several AER based chips to compose a powerful processing
system. The problem was discussed in the Neuromorphic Engineering Workshop of 2006. The platform is based
basically on an embedded computer, a powerful FPGA and serial links, to make the system faster and be stand alone
(independent from a PC). A new platform is presented that allow to connect up to eight AER based chips to a Spartan 3
4000 FPGA. The FPGA is responsible of the network communication based in Address-Event and, at the same time, to
map and transform the address space of the traffic to implement a pre-processing. A MMU microprocessor (Intel
XScale 400MHz Gumstix Connex computer) is also connected to the FPGA to allow the platform to implement eventbased
algorithms to interact to the AER system, like control algorithms, network connectivity, USB support, etc. The
LVDS transceiver allows a bandwidth of up to 1.32 Gbps, around ~66 Mega events per second (Mevps).
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) convert conventional frame-based video stream in the computer into AER and inject it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. This paper addresses the problem of converting, in a computer, a conventional frame-based video stream into the spike event based representation AER. There exist several proposed software methods for synthetic generation of AER for bio-inspired systems. This paper presents a hardware implementation for one method, which is based on Linear-Feedback-Shift-Register (LFSR) pseudo-random number generation. The sequence of events generated by this hardware, which follows a Poisson distribution like a biological neuron, has been reconstructed using two AER integrator cells. The error of reconstruction for a set of images that produces different traffic loads of event in the AER bus is used as evaluation criteria. A VHDL description of the method, that includes the Xilinx PCI Core, has been implemented and tested using a general purpose PCI-AER board. This PCI-AER board has been developed by authors, and uses a Spartan II 200 FPGA. This system for AER Synthetic Generation is capable of transforming frames of 64x64 pixels, received through a standard computer PCI bus, at a frame rate of 25 frames per second, producing spike events at a peak rate of 107 events per second.
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) inject a sequence of events at some point of the AER structure. This is necessary for testing and debugging complex AER systems.
This paper presents a PCI to AER interface, that dispatches a sequence of events received from the PCI bus with embedded timing information to establish when each event will be delivered. A set of specialized states machines has been introduced to recovery the possible time delays introduced by the asynchronous AER bus. On the input channel, the interface capture events assigning a timestamp and delivers them through the PCI bus to MATLAB applications. It has been implemented in real time hardware using VHDL and it has been tested in a PCI-AER board, developed by authors, that includes a Spartan II 200 FPGA. The demonstration hardware is currently capable to send and receive events at a peak rate of 8,3 Mev/sec, and a typical rate of 1 Mev/sec.
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