KEYWORDS: Field programmable gate arrays, Prototyping, Data compression, Clocks, Monte Carlo methods, Space operations, Calibration, Stars, Telecommunications, Atrial fibrillation
Future space missions are based on a new generation of instruments. These missions find a serious constraint in the
telemetry system, which cannot download to ground the large volume of data generated. Hence, data compression
algorithms are often mandatory in space, despite the modest processing power usually available on-board. We present
here a compact solution implemented in hardware for such missions. FAPEC is a lossless compressor which typically
can outperform the CCSDS 121.0 recommendation on realistic data sets. With efficiencies higher than 90% of the
Shannon limit in most cases - even in presence of noise or outliers - FAPEC has been successfully validated in its
software version as a robust low-complexity alternative to the recommendation. This work describes the FAPEC
implementation on an FPGA, targeting the space-qualified Actel RTAX family. We prove that FAPEC is hardwarefriendly
and that it does not require external memory. We also assess the correct operation of the prototype for an initial
throughput of 32 Mbits/s with very low power consumption (about 20 mW). Finally, we discuss further potential
applications of FAPEC, and we set the basis for the improvements that will boost FAPEC performance beyond the
100 Mbit/s level.
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