We have developed a high-resolution x-ray microscope with spatial resolution better than 100 nm. The utilized x-ray energy of the microscope is 17.5 keV that can penetrate through standard silicon substrate and enables to observe embedded nanoscale metal structure and defects, nondestructively. We have applied the present x-ray microscope for investigating 3D flash memory devices and observed precise metal filling structure in there. In addition, defects in the circuit area were also found.
E-beam inspection based on voltage-contrast (VC) defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in e-beam image contrast indicates shorts, opens, and void defect inline inspection in the idle of production line. Meanwhile, accurate measurement of threshold voltage and the source–drain current is required to characterize memory cell through multilayers. However, in the subthreshold region of memory cell, VC is weakened due to gate voltage stimulated by electron dose of e-beam scanning. We developed a modulated beam imaging with the SEM vector scan system to enhance VC contrast and defect inspection capability. Reliability of the modulated electron microscopy is validated by comparing with physical probing test result for process variation of Boron doping and annealing conditions in full wafer processing. VC with the modulated electron microscopy is well correlated to the probing test result. Image contrast of the modulated microscopy can differentiate contact via on floating circuit and disconnected floating circuit. We applied the modulated electron microscopy for inline electrical defect detection at the middle of manufacturing line of integrated circuits. The defect distribution map by the modulated electron microscopy was confirmed to reproduce the physical probe test result. By achieving inline electrical characterization before back end of line, yield loss issues can be detected and characterized 2 weeks earlier than conventional method. Moreover, this ability to detect and characterize memory cell issues inline is supposed to contribute to overcome the yield learning cycle bottleneck.
E-beam inspection based on voltage-contrast defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in E-beam image contrast indicates shorts, opens and void defect inline inspection in the idle of production line. Meanwhile, accurate measurement of threshold voltage and the source-drain current is required to characterize memory cell through multi-layers. However, in the subthreshold region of memory cell, voltage contrast (VC) is weakened due to gate voltage stimulated by electron dose of e-beam scanning. We developed a modulated beam imaging with the SEM vector scan system to enhance VC contrast and defect inspection capability. Reliability of the modulated electron microscopy is validated by comparing with physical probing test result for process variation of Boron doping and annealing conditions in full wafer processing. VC with the modulated electron microscopy is well correlated to the probing test result. Image contrast of the modulated microscopy can differentiate contact via on floating circuit and disconnected floating circuit. We applied the modulated electron microscopy for in-line electrical defect detection at the middle of manufacturing line of integrated circuits. The defect distribution map by the modulated electron microscopy was confirmed to reproduce the physical probe test result. By achieving in-line electrical characterization before back end of line, yield loss issues can be detected and characterized two weeks earlier than conventional method. Moreover, this ability to detect and characterize memory cell issues inline is supposed to contribute to overcome the yield learning cycle bottleneck.
To fix the root cause of electrical failure chips, we do failure analysis by an electrical test. However, this analysis takes much long time because an electrical test is done after a few months since the defect occurred in in-line processes. To reduce the analysis time, we used the defects detected by in-line optical inspections of post semiconductor process steps. In order to identify the position of the defects that caused the failure, we used to match CAD contour with a DR-SEM (Defect Review-SEM) image contour of the defect. But the “hit rate” of the defect was not so high. Here hit rate is a rate that the defects cause an electrical failure chip. There were two reasons. First, the matching success rate was low because extracting contour from SEM is inaccurate. Second, CAD was a mask pattern and didn’t include the circuit node information, so there was an over-detection such as a short between dummy nodes. We propose a high precision in-line schematic failure analysis technique by machine learning and circuit node information. For matching pixel to pixel, we match Fake-SEM generated by GAN instead of CAD with DR-SEM. Next we make the CAD that is added the defect, and a design verification technique LVS generates circuit diagram. When the defect’s diagram is different from reference, we classify the defect cause an electrical failure. We confirmed that this technique could dramatically improve classification accuracy of the defect of root cause in manufacturing with our memory device.
A depth measurement technique for extremely deep holes (such as channel holes in 3D flash memory devices)—by using back-scattered-electron (BSE) images obtained by a high voltage critical dimension scanning electron microscope (CDSEM)— was developed. A high voltage CD-SEM can detect BSEs that penetrate solids surrounding deep holes. These BSE images include rich information concerning the bottom structures of deep holes. As the BSEs lose their energies according to the distance they travel in solids, it is deduced that the BSE image intensity at hole bottoms depends on hole depth. In a feasibility study on depth measurement using an SEM simulator, it was found that the intensity also depends on hole diameter. The relationship between BSE intensity, hole depth, and hole diameter was modeled by simplifying a backscattering model and approximating the target medium by volume density. Based on this model, a depth measurement technique using only a top-view BSE image is proposed. Measurement error of the technique for channel holes of a 3D flash memory device with depths of a few microns was evaluated by using a high voltage CD-SEM. According to the results of the evaluation, error range was 62 nm and measurement repeatability was ± 18 nm. It is concluded that these values are sufficient for detecting depth defects. This technique achieves fast and non-destructive depth measurement of individual extremely deep holes.
For robustness improvement of inline metrology tools, we propose inline reference metrology system “Verification Metrology System (VMS)”. This system combines inline metrology tools and non-destructive reference metrology tools. VMS can detect the false alarm error and the not-detectable error caused by measurement robustness decay of inline metrology tools. GI-SAXS was selected as the inline reference metrology tool. GI-SAXS has high robustness capability for under-layer structure changes. VMS with scatterometry and GI-SAXS was evaluated for measurement robustness. The potential to detect metrology system errors was confirmed using VMS. Cost reduction effect of VMS was estimated for the false alarm case. Total cost is obtained as a sum of the false alarm loss and the metrology cost. VMS is effective for total cost reduction with low sampling. And it is important that sampling frequency of reference metrology is optimized based on process qualities.
The aggressive device scaling imposed by the International Technology Roadmap for Semiconductors (ITRS) is
introducing additional and more demanding challenges to current in-line monitoring tools. In this paper we present a
new probe microscopy based technology, the Rapid Probe Microscope (RPM), which produces nano-scale images using
a height contrast mechanism in a non-vacuum environment. The system offers the possibility to address metrology
challenges in alternative ways to existing review and inspection tools. This paper presents applications of the RPM
process which cater to the requirements of the semiconductor industry. Results on several standard semiconductor wafer
layers have been used to demonstrate the capabilities of the RPM process, including nano-scale surface imaging at high
image capture rates.
KEYWORDS: Oxides, Scanning electron microscopy, Monte Carlo methods, Silicon, Silica, Wet etching, Inspection, Optical spheres, Electron beams, Data acquisition
As the candidates of factors to consider for accurate Monte Carlo simulation of SEM images, (1) the difference
of cross-section between an approximate shape for simple simulation and a real pattern shape, (2) the influence of native
oxide growing on a pattern surface, and (3) the potential distribution above the target surface are proposed. Each
influence on SEM signal is studied by means of experiments and simulations for a Si trench pattern as a motif. Among
these factors, native oxide of about 1nm in thickness has a significant influence that increases SEM signals at the top
edge and the slope. We have assumed and discussed models for the native oxide effect.
KEYWORDS: Monte Carlo methods, Scanning electron microscopy, Silica, Silicon, Electron beams, Dielectrics, Defect inspection, Optical simulations, Sensors, 3D modeling
CD-SEM measurement is the main measuring tool of critical dimensions (CD). CD-measurements involve
systematic errors that depend on SEM set-up and the pattern. In addition to systematic errors, charging of a
wafer plays an important role in CD-SEM and defect inspection tools. Charging dependence of secondary
electron emission coefficient which is one of the major charging parameters, was studied. Timing
characteristics were measured and then simulated using Monte Carlo model. The measurements and
simulations were done for a multiple number of frames and for imaging of a contact hole using pre-charge of
a large area. The results of simulation confirmed the measured results. The understanding of the effect helps
in tuning the settings of CD-SEM.
KEYWORDS: Monte Carlo methods, Silica, Scanning electron microscopy, Silicon, Optical simulations, Scattering, Electron beams, Laser scattering, Sensors, Electron transport
In semiconductor manufacturing, control of hotspots by optical proximity correction (OPC) requires
accurate measurements of shapes and sizes of fabricated features. These measurements are carried
out using CD-SEM. In order to measure 2D shapes, edges of features should be clearly defined in all
directions. Positions of edges are often unclear because of charging. Depending on the SEM setup and
the pattern under measurement, the effect of charging varies. The influence of measurement conditions
can be simulated and optimized. A Monte Carlo electron-beam simulation tool was developed, which
takes into account electron scattering and charging. CD-SEM imaging of SiO2 lines on Si were studied.
In experiment, an effect of contrast tone reversal was found, when beam voltage was varied. The same
effect was also found in simulations, where contrast reversal was similar to the experimental results. The
time dependence of contrast variation was also studied. A good agreement between simulation and
measurement was found. The simulation software proved reliable in predicting SEM images, which
makes it an important tool to optimize settings of electron-beam tools. Based on such simulations,
optimum conditions of SEM setup can be found.
KEYWORDS: Critical dimension metrology, Optical simulations, Electron beams, Monte Carlo methods, Silicon, Scanning electron microscopy, Scattering, Laser scattering, Oxides, Atomic force microscopy
In recent year, CD metrology is required not only precision but also accuracy for more accurate CD control.
CD bias between CD-SEM and a reference tool is the most important factor for more accurate CD measurement. CD
bias varies by many CD-SEM and pattern condition. Then, CD bias variation caused by CD-SEM should be evaluated
in detail. However, it is difficult to estimate these factors dependence on CD bias variation experimentally. Then, we
develop an electron beam simulator with charging effects. We evaluated the mechanism of CD bias variation using
electron beam simulator and CD-SEM data. As the results, CD bias variation is caused by changing of secondary
electron signal which depends on space width. There are several different points between the experimental results and
the simulation results in grayscale line profiles. Simulation data can be more similar to experimental data with charging
effects and the actual experimental conditions. Simulation has enough capability to estimate CD bias variation with the
simple structure and non-charging calculation. And mechanism of space width dependence on CD bias can be analyzed
by using electron beam simulator.
Necessity of nondestructive three-dimensional measurement methodology has increased. We propose three-dimensional measurement by CD-SEM with T-MOL (Tilting and Moving Objective Lens) electron optics system. We designed the new objective lens, and confirmed that the new electron optics system provides 3.0nm resolution at tilting angle of 10 degrees. Moreover, we developed the multi-matching technique based on the several stereographical tilted images. In this paper, we report the comparison between the new technique and the conventional one, as well as the technique’s capability using the actual semiconductor devices.
KEYWORDS: Objectives, 3D metrology, Image resolution, 3D image processing, Semiconductors, Reconstruction algorithms, 3D image reconstruction, Magnetism, Electron beams, Optical simulations
We report about three-dimensional measurement by CD-SEM. Last year, we reported that the new T-MOL (Tilting and Moving Objective Lens) electron optical system enabled the capture of tilt images without deterioration of the resolution and confirmed that the T-MOL system provides 4 nm resolution at tilting angle 5 degrees. In this year we developed and evaluated the new objective lens and the new octapole deflector for increase of tilting angle and improvement in resolution, and we confirmed that the new electron optical system provides 3.6 nm resolution at tilting angle 8 degrees. Moreover, we report the optimization of the stereo matching technique based on the tilting picture using the actual semiconductor device for measurement 3D analysis.
A new mask methodology of mask defect specifications by fail-bit-map (FBM) analysis of LSI devices was proposed. In this paper, concept of new mask defect specifications based on the FBM analysis is shown and impacts on LSI devices of mask defects are studied and the new methodology for next generation is applied.
The new mask defect specifications were implemented in a gate-level mask with defects programmed into a 0.175μm-rule DRAM fabrication process, as follows, Firstly, the programmed defects varied in terms of the types, locations and sizes were designed into the memory cell area on the 0.175μm-rule DRAM gate-level mask. Secondly, the gate-level mask with programmed defects was fabricated with conventional mask process flow and the actual mask defect sizes were measured. Thirdly, exposures of the gate-level mask were carried out with conventional 0.175μm-rule DRAM process. Finally, the large impacts on CDs caused by mask defect printability on wafers were clarified and FBM analysis was performed to characterize the relationship among the actual mask defect variations, the CD variations and electrical function of 0.175μm-rule DRAM. This relationship can facilitate determination of the mask defect specifications on 0.175μm-rule DRAM and also likely contribute to estimate next-generation defect specifications.
According to the results of the above procedure, the mask defect specifications for opaque defects should be generally tighter than those for clear defects in view of the printability on the wafers and the FBM analysis. Nevertheless, the FBM results suggested that current mask inspection sensitivity for clear defects was too high. With the new methodology, in regard to the impacts of mask defects not only on wafer CDs but also on LSI devices, we have succeeded in obtaining useful results for the mask defect specifications.
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