In the sub-7 nm technology nodes, the cost of printing dense via layers increases dramatically. Directed self-assembly (DSA) (DSA) technology with multiple patterning (MP) lithography (DSA-MP) provides a high-volume manufacturing solution with a high throughput and low cost. To enable the technology, a high-quality DSA-MP-aware layout decomposer that contains DSA grouping and MP assignment is necessary. We propose a graph-based heuristic algorithm that minimizes the potential DSA decomposition violations using grouping nodes in the complete graph and the corresponding place-and-route method. Then the grouping result is modified and the MP assignment is solved simultaneously by hybrid algorithms. Experimental results show the efficiency and effectiveness of the proposed method in dealing with large dense vias patterns.