Editor-in-Chief Harry Levinson looks back on 2021.

This is a list of reviewers who served the Journal of Micro/Nanopatterning, Materials, and Metrology in 2021.

We identify and describe categories of fluorochemicals used to produce advanced semiconductors within the lithographic patterning manufacturing processes. Topics discussed include the per- and polyfluoroalkyl substance (PFAS) materials used and their necessary attributes for successful semiconductor manufacturing, consisting of photoacid generators, fluorinated polyimides, poly(benzoxazole)s, antireflection coatings, topcoats, and embedded barrier layers, fluorinated surfactants, and materials for nanoimprint lithography. In particular, an explanation is given of the particular function that these PFAS materials contribute. It is noted that in almost all cases fluorine-free alternatives are very unlikely to provide the essential properties present in PFAS systems. Nonfluorinated alternative compounds are discussed where available. Finally, a summary table is provided listing the families of materials discussed, the critical purpose served, what the PFAS compound provides, and the prospects for alternatives.

Guest editors Doug Resnick and Eric Panning introduce the Special Section on Novel Patterning Technologies II.

We have developed multi-field imprint (MFI) technology to improve the productivity of for nano-imprint lithography (NIL). Using a template having an imprinting size of 46  mm  ×  28  mm for MFI and the latest NIL system NZ2C (Canon Corp.), we successfully achieved MFI on a 300-mm wafer. The throughput being equivalent to 160 wafers per hour was demonstrated using throughput enhancement solutions, such as gas permeable spin-on-carbon and multi field dispense. The overlay accuracy around 7 nm was also obtained. In this report, we’ll report about the performance of MFI technology: patterning ability, throughput, and overlay accuracy, and discuss the future outlook.

Background: High-density interconnect (HDI) printed circuit board (PCB) packaging technology has gained greater significance in military and aerospace sectors. Manufacturing with fineline features and the impedance-controlled circuit pattern is a major technical challenge for which several methods have been reported.

Aim: Herein, a novel process of HDI PCB fabrication has been presented using liquid photosensitive resist spray coating followed by digital micromirror device (DMD)-based micro-opto-electromechanical direct imaging photolithography to realize fineline circuit pattern.

Approach: A fineline HDI circuit has been developed with minimum conductor trace width of <40  μm and spacing from the copper foil (18-μm thickness) cladded to dielectric substrate that comply the requirements of high reliability space electronics packaging. Such fineline conductor features have been exemplified with optical microscopy, SEM, and subjected to micro-sectioning.

Results: The resulting undercut values and etched pattern have been found to be excellent. Leveraging the standard test method, the peel strength values of the realised fineline circuit patterns were measured to be more than 1.2  kg  /  cm² required for high reliability space electronics packaging applications.

Conclusions: The output paraments meet the space high-reliability requirements withstanding the stringent environmental conditions of ultra-high vacuum, vibration, and the extreme temperatures for longer durations.

Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposures of a low-viscosity resist deposited by jetting technology onto the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Previous studies have demonstrated NIL resolution better than 10 nm, making the technology resolution suitable for the patterning of several generations of critical memory levels with a single mask.

Overlay is critical for advanced memory devices such as dynamic random-access memory and phase change memory. Both device types continue to scale, with expected half pitches down to 14 nm and beyond. Typical overlay budgets are on the order of 20% of the half pitch, meaning overlay requirements of <3  nm. Previously, we have employed systems (such as high-order distortion correction) to improve upon higher order distortion errors, thereby improving the overlay performance of our process.

Some process variables that are unique to NIL and that can be considered as process tunable variables include imprint force and tip/tilt of the imprint head relative to the wafer. These were identified to be significant variables to further improve the overlay and to achieve good overlay stability in a production run at throughput. We introduce these overlay tuning knobs for NIL and present the techniques and models to achieve stability of imprint force and tip/tilt in order to reduce both wafer to wafer variation as well as the field–field variation of these variables. Applying these techniques enables NIL to meet the overlay requirements for advanced memory device production.

Computational technologies are still in the course of development for nanoimprint lithography (NIL). Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their daily toolbox. The most challenging issue in NIL process simulation is the scale difference of each component of the system. The template pattern depth and the residual resist film thickness are generally of the order of a few tens of nanometers, whereas the process needs to work over the entire shot size, which is typically of the order of several hundred square millimeters. This amounts to a scale difference of the order of 10⁶. Therefore, in order to calculate the nanoimprint process with conventional fluid structure interaction simulators, an enormous number of meshes is required, which results in computation times that are unacceptable. We introduce a process simulator which directly inputs the process parameters, simulates the whole imprinting process, and evaluates the quality of the resulting resist film for jet and flash imprint lithography process. To overcome the scale differences, our simulator utilizes analytically integrated expressions which reduce the dimensions of the calculation region. In addition, the simulator can independently consider the resist droplet configurations and calculate the droplet coalescence, thereby predicting the distribution of the non-fill areas which originate from the trapped gas between the droplets. The simulator has been applied to the actual NIL system and some examples of its applications are presented here.

To improve the throughput of inkjet-type nanoimprint lithography, reduction of a resist filling times is essential. Highly permeable underlayer films reduce the resist filling time by rapidly defoaming trapped gas. The gas permeability of helium and air in several conventional underlayer films was experimentally evaluated by measuring defoaming speeds; however, the use of helium is an expensive solution. The defoaming speed of a particular underlayer film and air was found to be about three times faster than a conventional underlayer film and helium. Validating this combination of film and gas, a throughput of over 100 wafers per hour and low-cost operation in air were realized without deteriorating the underlayer’s performance as a hard mask. Understanding the theoretical background of the interactions between underlayer films and gases enabled us to realize an underlayer film with high gas permeability for the air.

Different technologies have been explored for fabricating silicon nanopillars (SiNPs). One of the emerging technologies is the combined fabrication process based on silica nanoparticle lithography and metal-assisted chemical etching (MACE). However, the process flow to fabricate successfully SiNPs depends on various technology factors. We report investigations on factors affecting the fabrication technology, from the assembly of close-packed silica nanoparticle monolayers using drop-coating method, formation of nonclose packed silica nanoparticle monolayers using HF vapor etching, to creation of SiNPs using MACE. Etching mechanisms are suggested to explain observed experiment results.

To improve the productivity of nanoimprint lithography (NIL) in semiconductor manufacturing, we have developed spin-coating and flash imprint lithography (SC-FIL). Using a newly developed SC-FIL resist, we imprinted a 300-mm-wide whole wafer including partial fields. The cross-sectional image showed a well-shaped half-pitch dense line with a width of 26 nm. The mix-and-match overlay accuracy (3σ) was 3.9 nm in the X direction and 3.4 nm in the Y direction. Assuming Washburn’s model of capillary flow, we identified the unique defect-generation mechanism in SC-FIL and hence optimized the SC-FIL process for high throughput and low defect density. After optimizing the NIL, the multimodule NZ2C system with four imprint heads is expected to achieve a throughput of 124 wafers per hour and a defectivity of only 0.005  defects per cm².

Background: Integrated circuits are fabricated layer by layer. It is crucial to their performance that these layers are well aligned to each other, and any undesired translation of a layer is called overlay. Thus far, overlay measurements have been limited to visible wavelengths, but the use of materials that are opaque to visible wavelengths necessitates measurements using infrared light.

Aim: We set out to demonstrate that an overlay sensor based on digital holographic microscopy can perform such overlay measurement at infrared wavelengths, while maintaining functionality at visible wavelengths.

Approach: This was done by constructing a breadboard setup that is capable of measuring overlay at wavelengths ranging from 400 to 1100 nm.

Results: Using the setup, we demonstrated good linearity between an applied amount of overlay and the measured amount. In addition, we demonstrated that the setup is only sensitive to structures at the top of the wafer. Measurements are therefore unaffected by the fact that Si is transparent at 1100 nm.

Conclusions: These results demonstrate the viability of an overlay sensor that is sensitive to visible and infrared light, allowing more freedom in choice of materials for integrated circuits.

Background: A local tilt angle of <300  mrad results in a critical dimension uniformity (CDU) impact below 0.1 nm when a pellicle is used for extreme ultraviolet (EUV) lithography. However, the thermomechanical property guidelines satisfying this specification have not yet been established.

Aim: We present the thermomechanical property guidelines that yield a CDU impact below 0.1 nm.

Approach: The peak temperature ranges of the EUV pellicle, as a function of the emissivity, were calculated through experimental, numerical, and finite element method analyses. The wrinkle profiles were evaluated as a function of the coefficient of thermal expansion (CTE) within these temperature ranges. The emissivity and CTE values satisfying the specifications were obtained using the CDU impact caused by the wrinkled EUV pellicle.

Results: The wrinkle amplitude in the EUV pellicle exhibited 45% attenuation with a twofold decrease in the CTE. The maximum local tilt angles for the 17, 16, and 15 nm half-pitch patterns were 290.2, 286.1, and 272.3 mrad, respectively. CTE below 2  ×  10^−  5  K^−  1 and emissivity above 0.1 are suggested for the EUV pellicle.

Conclusions: The CTE and emissivity guidelines satisfying the CDU impact specifications can be used for developing next-generation EUV pellicles.