Lithographic challenges and their solutions for critical layers in sub-14nm node logic devices

Tsann-Bim Chiou; Mircea Dusa; Alek C. Chen; David Pietromonaco

doi:10.1117/12.2025863

12 April 2013 Lithographic challenges and their solutions for critical layers in sub-14nm node logic devices

Tsann-Bim Chiou, Mircea Dusa, Alek C. Chen, David Pietromonaco

Proceedings Volume 8683, Optical Microlithography XXVI; 86830R (2013) https://doi.org/10.1117/12.2025863
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

When the technology node of logic devices is sub-14nm, finding lithographic solutions for most of the critical layers is challenging. For instance, metal 1 interconnect layer is one of the most lithographically difficult layers in a logic design, not only owing to its two-dimensional topology with irregular geometric shapes but also owing to the small minimum pitches in two orientations. A double pattern technology with 193nm immersion is insufficient to resolve the critical features at the minimum pitch. Only 23% cell shrinkage, with respect to a 16/14nm-node design, is predicted by examining most of the crucial lithographic metrics. To archive an expected cell shrinkage of approximately 50% for the next node, immersion technology with more than a double split pitch, such as triple patterning technology, appears to be able to drive the minimum pitch to satisfy sub-14nm-node lithographic requirements; however, process complexity and cost are unavoidably higher. Analyses herein of the lithographic metrics reveal that a common process window and CD uniformity do not fully suffice for the lithographic process. The main cause of this failure is a very large best focus shift among the critical features due to the 3D mask effect. Reducing the wavelength of the light source to 13.5nm in the extreme ultraviolet range dramatically improves image resolution, the process window and the CD uniformity even with traditional illumination source shapes. Selection of lithographic solution for each critical layer is relevant, considering image performance, design style and constraints, process integration, running cost, and other factors.

Citation Download Citation

Tsann-Bim Chiou, Mircea Dusa, Alek C. Chen, and David Pietromonaco "Lithographic challenges and their solutions for critical layers in sub-14nm node logic devices", Proc. SPIE 8683, Optical Microlithography XXVI, 86830R (12 April 2013); https://doi.org/10.1117/12.2025863

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